ADN2806 Analog Devices, Inc., ADN2806 Datasheet
ADN2806
Related parts for ADN2806
ADN2806 Summary of contents
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... This device, together with a PIN diode, TIA preamplifier, and a lim amp can implement a highly integrated, low cost, low power fiber optic receiver. The ADN2806 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN LOL ...
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... ADN2806 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 3 Output and Timing Specifications ............................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Timing Characteristics..................................................................... 6 Pin Configuration and Function Descriptions............................. Interface Timing and Internal Register Description............. 8 REVISION HISTORY 2/06— ...
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... PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth Jitter Peaking Jitter Generation Jitter Tolerance 1 Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure. = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2 F Conditions @ PIN or NIN, dc-coupled PIN − NIN ...
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... ADN2806 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High Output Voltage Low Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs’ Timing Rise Time Fall Time Setup Time Hold Time INTERFACE DC CHARACTERISTICS ...
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... Exposure to absolute 125°C maximum rating conditions for extended periods may affect −65°C to +150°C device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-lead LFCSP, 4-layer board with exposed paddle soldered to VEE, θ = 28°C/W. JA Rev Page ADN2806 ...
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... ADN2806 TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R LOAD 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev Page DIFF ...
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... Disable Clock and Data Outputs. Active high. LVTTL. DO Differential Recovered Data Output. LVDS. DO Differential Recovered Data Output. LVDS. P Phase Detector, Phase Shifter GND. P Phase Detector, Phase Shifter Power. Connect to VCC. P Connect to GND. Rev Page VCC 23 VEE SDA 20 SCK 19 SADDR5 18 VCC 17 VEE ADN2806 ...
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... ADN2806 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 A5 SCK S SLADDR[4... SDA t SCK S SLAVE ADDRESS [6... MSB = 1 SET BY PIN 19 Figure 6. Slave Address Configuration ...
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... System Reset D5 D4 Write a 1 followed by Set reset ADN2806 SQUELCH Mode Set to 0 Set Squelch data outputs and clock outputs 1 = Squelch data outputs or clock outputs Rev Page ADN2806 D1 D0 LSB LSB ...
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... ADN2806 JITTER SPECIFICATIONS The ADN2806 CDR is designed to achieve the best bit- error-rate (BER) performance and to exceed the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where bit period ...
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... THEORY OF OPERATION The ADN2806 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops, which share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter ...
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... ADN2806 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger ...
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... LOL bit. If there is ever an occurrence of a loss-of-lock condition, this bit is internally asserted to logic high. The MISC[4] bit remains high even after the ADN2806 has reacquired lock to a new data rate. This bit can be reset by writing a 1 followed Register Bit CTRLB[6]. Once reset, the MISC[4] bit remains deasserted until another loss-of-lock condition occurs ...
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... Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2806 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADN2806 has eight subaddresses to enable the user-accessible internal registers (see Table 6 through Table 10) ...
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... MHz, and CTRLA[5:2] is set to [0101], that is, 5, because 622.08 Mbps/19.44 MHz = 2 In this mode, if the ADN2806 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2806 is operating in lock-to-reference mode, ...
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... The accuracy error of the reference clock is added to the accuracy of the ADN2806 data rate measurement. For example 100 ppm accuracy reference clock is used, the total accuracy of the measure- ment is within 200 ppm. ...
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... Use μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between ADN2806 supply pins VCC and VEE, as close as possible to the ADN2806 VCC pins. VCC + 22µ ...
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... PDJ pspp (<0.01 UI p-p typical the rise time, which is equal to 0.22/BW, r where BW ~ 0.7 (bit rate). Note that this expression for t The output rise time for the ADN2806 is ~100 ps regardless of the data rate. Rev Page −t/τ ); therefore, τ = 12t (−nT/RC − e )/0 ...
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... EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2806. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. ...
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... ADN2806ACPZ-500RL7 −40°C to +85°C 1 ADN2806ACPZ-RL7 −40°C to +85°C EVAL-ADN2806EB Pb-free part. 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © ...