AD5560 Analog Devices, Inc., AD5560 Datasheet - Page 37

• Manufacturer Part Number: AD5560
• Description: 1.2 A Programmable Device Power Supply With Integrated 16-bit Level Setting Dacs
• Manufacturer: Analog Devices, Inc.

10. Calculate F
11. If F
12. If R
13. Otherwise, this is a troublesome window in which a load
ADJUSTING THE AUTOCOMPENSATION MODE
The autocompensation algorithm assumes that there is 1 Ω of
resistance (R
application has resistance that differs greatly from this, then
it is likely that the autocompensation algorithm is nonoptimal.
If using the autocompensation algorithm as a starting point,
consider that overstating the C
the ESR R
oscillations. Understating C
to slow things down and reduce phase margin but not create
an oscillator.
It is often advisable to err on the side of simplicity. Rather than
insert a pole and zero at similar frequencies, it may be better to
add none at all. Set R
AD5560 bandwidth.
DEALING WITH PARALLEL LOAD CAPACITORS
In the event that the load capacitance consists of two parallel
capacitors with different ESRs, it is highly likely that the overall
complex impedance at the unity gain bandwidth is dominated
by the larger capacitor and its ESR. Assuming that the smaller
capacitor does not exist normally is a safer simplifying assump-
tion.
1/(2πRcCr).
AD5560. Ignore it with R
algorithm
cancel the load pole with R
frequency of 2 × F
choose the R
logarithmic scale. This ends the algorithm
pole and a load zero can’t be ignored. Use the following
steps:
•
•
•
P
C
To cancel the load pole at F
frequency of 6 × F
2 × F
wrong with miscalculation). Then choose the R
value that gives the closest zero to this ideal frequency
of 6 × F
To cancel the ESR zero at F
frequency of 2 × F
Then choose the R
to this ideal frequency of 2 × F
This ends the algorithm
> Fug, the load pole is above the bandwidth of the
< (R
C
is likely to give a faster response but could cause
C
) from the AD5560 to the DUT. If a particular
0
P
/25), then the ESR is negligible. Attempt to
Z
suggested earlier, but there is more that can go
, the ESR zero frequency, using F
P
Z[2:0]
on a logarithmic scale.
P[2:0]
value that gives the closest frequency on a
P
for some safety margin and then
= R
P
Z
R
P[2:0]
.
Z[2:0]
(this is more conservative than the
and overstating R
Z[2:0]
R
Z
value that gives the closest pole
capacitance and understating
= 0 to push them beyond the
zero. Choose an ideal zero
= 0, R
Z
P
, choose an ideal pole
, choose an ideal zero
Z
on a logarithmic scale.
P[2:0]
= 0. This ends the
C
is more likely
Z
=
Z[2:0]
Rev. B | Page 37 of 60
A more complex alternative is to calculate the overall impedance
at the expected unity gain bandwidth and use this to calculate
an equivalent series C
impedance at that particular frequency.
DAC LEVELS
This device contains all the dedicated DAC levels necessary
for operation: a 16-bit DAC for the force amplifier, two 16-bit
DACs for the clamp high and low levels, two 16-bit DACs for
the comparator high and low levels, a 16-bit DAC to set a
programmable open sense voltage, and a 16-bit offset DAC
to bias or offset a number of DACs on chip (FORCE, CLL,
CLH, CPL, CPH).
FORCE AND COMPARATOR DACS
The architecture of the main force amplifier DAC consists of
a 16-bit R-2R DAC, whereas the comparator DACs are resistor-
string DACs followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity.
The 16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off before being fed to the output amplifier.
The comparator DAC is similarly arranged. The force and
comparator DACs have a 25.62 V span, including overrange
to enable offset and gain errors to be calibrated out.
The transfer function for these 16-bit DACs is
where DAC CODE is X2 (see the Offset and Gain Registers
section).
CLAMP DACS
The architecture of the clamp DAC consists of a 16-bit resistor-
string DAC followed by an output buffer amplifier. This resistor-
string architecture guarantees DAC monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier.
The clamp DACs have a 25.62 V span, including overrange, to
enable offset and gain errors to be calibrated out.
V
⎛
⎜
⎝
OUT
OFFSET
=
. 5
125
_
×
DAC
2
VREF
16
R
_
and R
CODE
×
⎛
⎜
⎝
DAC
C
⎞
⎟
⎠
that have the same complex
2
+
CODE
16
DUTGND
⎞
⎟
⎠
−
. 5
125
×
VREF
AD5560
×