S1F76540MOC Epson Electronics America, Inc., S1F76540MOC Datasheet - Page 28

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S1F76540MOC

Manufacturer Part Number
S1F76540MOC
Description
Charge Pump Type Dc/dc Converter
Manufacturer
Epson Electronics America, Inc.
Datasheet
9.7 Parallel Connection (Boosting Capacity Increase)
voltage. Connecting n S1F76540s in parallel sets the boosting output impedance to approximately 1/n. Only the
smoothing capacitor CO for boosting output can be shared even in parallel connection.
multiple regulators in parallel will generate the reactive consumption current.)
in parallel.
S1F76540M0C Series Technical Manual (Rev.1.0)
Master IC
The parallel connection is effective when lowering the boosting output impedance or reducing the ripple
Using the regulator allows you to operate only one of n S1F76540s that are connected in parallel. (Running
Fig.9.8 shows a “quadruple boosting + regulator” connection example where two S1F76540s are connected
V
DD
+
Master IC
enables you to stop boosting the master and slave ICs; however, the regulator in the slave IC does not
stop.
POFF1X = L and POFF2X = L.
VI
Fig.9.8 Setting conditions
Power-off method
Other setting conditions
CO
Internal clock : ON (Low output mode)
Booster
Regulator
In the connection example shown in Fig.9.8, setting S1F76540 in the master IC to POFF2X = L (VI)
When |V
When placing the V
CI
When using the high output mode
Connect the FC pin in the master IC to VI.
When changing the temperature coefficient CT
Change the TC1 and TC2 pins in the slave IC as shown in Table 5.3.
+
1
2
3
4
5
6
7
8
REG
VO
VRI
V
RV
V
FC
TC1
TC2
| is greater than |VI|, the voltage that is equivalent to VI is generated in the V
REG
DD
: ON
: OFF
POFF1X
POFF2X
REG
C2N
C3N
C1N
C2P
C1P
pin into the high impedance state, set both the master and slave ICs to
Fig.9.8 Parallel connection example
VI
9. REFERENCE: EXTERNAL CONNECTION EXAMPLES
16
15
14
13
12
11
10
9
C2
C1
+
+
C3
+
EPSON
Slave IC
Internal clock : OFF (Clocks supplied from master IC)
Booster
Regulator
R1
+
CREG
R2
: ON
: ON (Select CT0 = -0.05%/°C.)
V
REG
1
2
3
4
5
6
7
8
VO
VRI
V
RV
V
FC
TC1
TC2
Slave IC
REG
DD
POFF1X
POFF2X
C2N
C3N
C1N
C2P
C1P
VI
16
15
14
13
12
11
10
9
REG
C2’
C1’
+
pin.
+
C3’
+
25

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