IKCS12G60DC Infineon Technologies Corporation, IKCS12G60DC Datasheet - Page 7

• Manufacturer Part Number: IKCS12G60DC
• Description: Control Integrated Power System Cipos?
• Manufacturer: Infineon Technologies Corporation

A minimum deadtime insertion of typ 380ns is also
provided, in order to reduce cross-conduction of
the external power switches.
EN, /FAULT (Pin 21)
The signal applied to pin EN controls directly the
output stages. All outputs are set to LOW, if EN is
at LOW logic level. The internal structure of the
pin is the same as Figure 2 made exception of the
switching levels of the Schmitt-Trigger, which are
here V
typical propagation delay time is t
pulldown resistor of typ. 75kΩ keeps the system
off in case of lack of control signal.
This pin is also used for indication of exceptional
conditions, such as overcurrent or undervoltage of
the control section of the gate drive IC. The on-
resistance of the internal open-drain FET is
typically 56Ω.
TEMP (Temperature monitor, Pin 22)
The integrated NTC-resistor is given in section
Integrated Components.
ITRIP (Over-current detection, Pin 13)
The overcurrent signal is provided by the
integrated shunt resistor. CIPOS™ provides an
over-current detection function. The integrated
ITRIP comparator threshold (typ 0.46V) is
referenced to VSS ground. An input noise filter
(typ: t
false
detection generates a hard shut down of all
outputs of the gate driver after the propagation
delay of typically 900ns.
As soon as the overcurrent detector triggers, the
/FAULT signal is activated, which pulls down the
enable pin.
VDD, VSS (control side supply and reference,
Pin 14, 23)
VDD is the low side supply and it provides power
both to input logic and to low side output power
Data Sheet
From µC
Figure 3: Internal Circuit at pin EN
ITRIPMIN
EN
/FAULT
EN,TH+
over-current
+5V
CiPoS™
= 225ns) prevents the driver to detect
= 2.1 V and V
≈ 50
Ω
VCC
U
events.
Z
=10.5V
SWITCH LEVEL
V
V
EN,TH-
EN,TH+
EN,TH-
>1
The
EN
INPUT NOISE
= 1.3 V. The
= 900 ns. A
FILTER
over-current
from overcurrent
from uv-detection
7/18
stage. Input logic is referenced to VSS ground as
well as the under-voltage detection circuit.
The under-voltage circuit enables the device to
operate at power on when a supply voltage of at
least a typical voltage of V
least present.
The IC shuts down all the gate drivers power
outputs, when the VCC supply voltage is below
V
switches from critically low gate voltage levels
during on-state and therefore from excessive
power dissipation.
VB1,2,3 and VS1,2,3 (High side supplies, Pin 1,
2, 4, 5, 7, 8)
VB to VS is the high side supply voltage. The high
side circuit can float with respect to VSS following
the
emitter/source voltage.
Due to the low power consumption, the floating
driver stage is supplied by an integrated bootstrap
circuit connected to VDD. This includes also
integrated bootstrap capacitors of 100 nF at each
floating supply, which are located very close to the
gate drive circuit.
The under-voltage detection operates with a rising
supply threshold of typical V
falling threshold of V
Figure 4.
VS1,2,3 provide a high robustness against
negative voltage in respect of VSS of -50 V. This
ensures very stable designs even under rough
conditions.
V+ (positive bus input voltage, Pin 10)
The high side IGBT are connected to the bus
voltage. It is recommended, that the bus voltage
does not exceed 500 V.
Sh (shunt negative potential, Pin 12)
This pin is the available terminal of the shunt
resistor, which is usually connected to the
reference voltage of CIPOS™.
Figure 4: Input filter timing diagram
DDUV-
external
= 10.4 V. This prevents the external power
high
CIPOS™ IKCS12G60DA
DDUV-
side
= 10.4 V according to
Rev. 2.3, March 2009
DDUV+
BSUV+
IKCS12G60DC
power
= 12.1 V and a
= 12.1 V is at
device