BU8272GUW ROHM Co. Ltd., BU8272GUW Datasheet - Page 15

• Manufacturer Part Number: BU8272GUW
• Description: Gpio Expander Ic
• Manufacturer: ROHM Co. Ltd.

● The Setting Registers
When setting address is written beyond 00h~09h, the register address will be forced to value 00h.
When the final address is set to 09h, then the next address 00h will be written.
By making XRST “Low”, the setting register value will be initialed shown in following register map.
1. Register map
2. Register functional explanations
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BU8272GUW
www.rohm.com
Addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
RWSEL15
RWSEL19
RWSEL16
RWSEL7
RWSEL0
RWSEL8
MASK15
MASK19
MASK16
GPIO15
GPIO19
GPIO16
IOSEL1
IOSEL2
INTSEL
MASK7
MASK0
MASK8
Symbol
GPIO7
GPIO0
GPIO8
～
～
～
～
～
～
～
～
～
00h
00h
00h
03h
Init
0fh
0fh
ffh
ffh
ffh
ffh
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
RWSEL7
RWSEL1
MASK15
GPIO15
MASK7
GPIO7
D7
5
-
-
-
-
00h
00h
00h
Init
0fh
Ffh
0fh
ffh
ffh
ffh
1h
1h
0h
RWSEL6
RWSEL1
MASK14
GPIO14
MASK6
GPIO6
Read or write data of GPIO bit 0 to 7.
Read or write data of GPIO bit 8 to 15.
Read or write data of GPIO bit 16 to bit 19.
In writing mode, 4 bits of MSB is ignored and in reading mode, 4 bits of
“0” is filled up from MSB.
0: Interrupt is not masked when “0” is written to GPIO bit 0 to 7
1: Interrupt is masked when “0” is written to GPIO bit 0 to 7
0: Interrupt is not masked When “0” is written to GPIO bit 8 to 15
1: Interrupt is masked When “0” is written to GPIO bit 8 to 15
0: Interrupt is not masked when “0” is written to GPIO bit 16 to 19
1: Interrupt is masked when “0” is written to GPIO bit 16 to 19
In writing mode, 4 bit of MSB is ignored and in reading mode, 4 bits of
“0” is filled up from MSB.
0: GPIO bit 0 through 7 becomes output mode.
1: GPIO bit 0 through 7 becomes input mode.
0: GPIO bit 8 through 15 becomes output mode.
1: GPIO bit 8 through 15 becomes input mode.
0: GPIO bit 16 through 19 becomes output mode.
1: GPIO bit 16 through 19 becomes input mode.
0: RWSEL bit 0 through 7 becomes available.
1: Change to pull-up mode.
0: RWSEL bit 8 through 19 becomes available.
1: Change to pull-up mode.
0: Make Interrupt “Low active”.
1: Make Interrupt “High active”.
D6
4
-
-
-
-
RWSEL5
RWSEL1
MASK13
GPIO13
MASK5
GPIO5
D5
3
-
-
-
-
15/17
RWSEL4
RWSEL1
MASK12
GPIO12
MASK4
GPIO4
D4
2
-
-
-
-
Description
RWSEL3
RWSEL1
MASK19
RWSEL1
MASK11
GPIO11
GPIO19
MASK3
GPIO3
D3
1
9
-
RWSEL2
RWSEL1
RWSEL1
MASK10
MASK18
GPIO10
GPIO18
INTSEL
MASK2
GPIO2
D2
0
8
RWSEL1
RWSEL9
RWSEL1
MASK17
GPIO17
MASK9
IOSEL2
MASK1
GPIO1
GPIO9
Technical Note
2009.09 - Rev.A
D1
7
RWSEL0
RWSEL8
RWSEL1
MASK16
GPIO16
IOSEL1
MASK0
MASK8
GPIO0
GPIO8
D0
6