BU9833GUL-W ROHM Co. Ltd., BU9833GUL-W Datasheet - Page 11

• Manufacturer Part Number: BU9833GUL-W
• Description: 256?8 Bit Electrically Erasable Prom
• Manufacturer: ROHM Co. Ltd.

◇CURRENT READ
◇RANDOM READ
◇SEQENTIAL READ
○ In case that the previous operation is Random or Current Read (which includes Sequential Read
○If an Acknowledge is detected, and no STOP condition is generated by the master (μ-COM),
NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become
○ Random Read operation allows the master to access any memory location indicated word
○If an Acknowledge is detected, and no STOP condition is generated by the master (μ-COM),
NOTE) If an Acknowledge is detected with "Low" level, not "High" level, command will become
○If an Acknowledge is not detected, the device will terminate further data transmissions
○If an Acknowledge is not detected, the device will terminate further data transmissions
SDA
LINE
address.
and await a STOP condition befere returning to the standby mode.
and await a STOP condition befere returning to the standby mode.
respectively), the internal address counter is increased by one from the last accessed address
(n). Thus Current Read outputs the data of the next word address (n+1).
If the last command is Byte or Page Write, the internal address counter stays at the last address
(n). Thus Current Read outputs the data of the word address (n).
the device will continue to transmit the data. ［It can transmit all data (2kbit 256word)］
the device will continue to transmit the data. ［It can transmit all data (2kbit 256word)］
Sequential Read. So the device transmits the next data, Read is not terminated. In the
Sequential Read. So the device transmits the next data, Read is not terminated. In the
case of terminating Read, input Acknowledge with "High" always, then input stop condition.
case of terminating Read, input Acknowledge with "High" always, then input stop condition.
S
T
A
R
T
SDA
LINE
1 0
ADDRESS
1
SLAVE
0
A
R
S
T
T
A2
1
0
0
0
W
W
Fig.-11 RANDOM READ CYCLE TIMING
R
T
R
E
/
Fig.-10 CURRENT READ CYCLE TIMING
I
ADRESS
1
SLAVE
C
A
K
0
WA
7
A2
ADDRESS（ｎ）
0
WORD
0
W
R
/
R
A
D
E
A
C
K
REV. A
D7
WA
0
A
C
K
S
T
A
R
T
DATA
1 0
ADDRESS
1
SLAVE
0
A2
D0
0
0
C
A
K
W
R
A
D
R
E
/
O
P
S
T
A
C
K
D7
DATA(n)
D0
C
A
K
O
S
T
P
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