HMP451S6MMP8C Hynix Semiconductor, HMP451S6MMP8C Datasheet - Page 3

• Manufacturer Part Number: HMP451S6MMP8C
• Description: 200pin Unbuffered Ddr2 Sdram So-dimms Based On 2gb Version
• Manufacturer: Hynix Semiconductor

Rev. 0.1 / May. 2008
PIN DESCRIPTION
CK[1:0], CK[1:0]
CKE[1:0]
S[1:0]
RAS, CAS, WE
BA[2:0]
ODT[1:0]
A[9:0], A10/AP,
A[15:11]
DQ[63:0]
DM[7:0]
DQS[7:0], DQS[7:0] In/Out
V
SDA
SCL
SA[1:0]
TEST
DD
, V
Symbol
DD
SPD,V
SS
Input
Input
Input
Input
Input
Input
Input
In/Out
Input
Supply
In/Out
Input
Input
In/Out
Type
Cross
Point
Active
High
Active
Low
Active
Low
Active
High
Active
High
Cross
point
Polarity
The system clock inputs. All adress an commands lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to
the input clock.
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,
RAS and WE define the operation to be excecuted by the SDRAM.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
During a Bank Activate command cycle, difines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is
high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP
is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in
conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn
are used to define which bank to precharge.
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading
edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS. If the module is to be operated in single ended
strobe mode, all DQS signals must be tied on the system board to VSS and DDR2
SDRAM mode registers programmed approriately.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to V
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to VDD to act as a pull up.
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
Selects which DDR2 SDRAM internal bank of four or eight is activated.
Data Input/Output pins.
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
DD t
Pin Description
o act as a pull up.
3