MP7680 Exar Corporation, MP7680 Datasheet
MP7680
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MP7680 Summary of contents
Page 1
... Four Quadrant Multiplication · Latch-Up Free GENERAL DESCRIPTIONS The MP7680 and the integrate four 12-bit four-quadrant- multiplying DACs with independent reference inputs and excellent matching characteristics. The MP7680 grades offer 1/2, 1 and 2 LSB of relative accuracy. The superior offers a low 2 LSB of gain error. ...
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... MP7680 DB11 - DB4 8 (MSB MUX 4 DB3 - DB0 1 (LSB) 4 B1/B2 Rev. 3.10 8-Bit Latch 12-Bit Latch 4-Bit Latch 8-Bit Latch 12-Bit Latch 4-Bit Latch 8-Bit Latch 12-Bit Latch 4-Bit Latch 8-Bit Latch 12-Bit Latch 4-Bit Latch 8 1 Input Latches DAC Latches Control Control ...
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... DB7 19 22 DB6 Pin PDIP , (0.600” See the following B1/B2 AO page for NC pin descriptions A1 XFER WR2 WR1 Pin PQFP 3 MP7680 A0 B1/ DGND AGND V REFD R FBD I OUT1D I OUT2D I OUT2C I OUT1C R FBC V REFC DB0 (LSB) DB1 DB2 ...
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... MP7680 PIN DESCRIPTION 40 Pin PDIP , CDIP PIN NO. NAME DESCRIPTION 1 A1 DAC Address Bit 1 2 XFER Transfer: Updates all DAC’s 3 WR2 Write 2: Gates the XFER Function 4 WR1 Write 1: Gates the DAC Selection 5 CS Chip Select Connection 7 V Reference Input for DAC A ...
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... IN V +10 + 2 LKG C 7 7.0 IN 100 50 50 100 5 MP7680 Otherwise Noted) Max Units Test Conditions/Comments Bits LSB Best Fit Straight Line Spec. (Max INL - Min INL LSB +2.0 +4.0 LSB Using Internal R FB +16 +16 +2 ppm/° ° C DGain/DTemperature +70 ppm/% ...
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... MP7680 ELECTRICAL CHARACTERISTICS Parameter SUPPL Y 4 POWER Functional Voltage Range Supply Current TIMING CHARACTERISTICS Write Pulse Width Chip Select Set-Up Time Address Set-Up Time Chip Select and Address Hold Time Latch Select Set-Up Time Latch Select Hold Time Data Valid Set-Up Time ...
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... XFER = Low . t 2. The timing of Figure 2. reproduces BH the conditions in any of the many possible t DH Theory XFER 2. W rite Cycle T iming (Each DAC) 7 MP7680 is the timing of the condition XFER = WR2 graphically that all control signals must meet writing cycles (see of Operation). ...
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... The logic that Figure 3. controls the writing of the input latches and the one that controls the DAC latches are completely separated easy to understand how the MP7680/80A works by understanding each basic operation. Rev. 3.10 INPUT LA TCHES LA11 - LA0 ...
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... It is possible to generate an 8-bit interface timing by replacing a single 12-bit write cycle ( ( Figure 5. DB3-DB0. High Cycles from Input Latches 9 MP7680 ) During the second cycle the condition B1/ with a double 8-bit write cycles Figure 4. ) 8-bit applications should ground inputs B1/B2 DATA to B1 ...
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... MP7680 Transferring Data to the DAC Latches Once one or all of the input latches have been loaded, the condition XFER = WR2= low transfers the content of ALL the input latches in the DAC latches. The output of the DAC latches (DA11-DA0) changes and the DAC current ...
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... Channel Output (+10 V MAX) + 10k 10k MP5010 + Right Channel Output (+10 V MAX) + Matched Pairs Figure 11 MP7680 V OUTA - OUTB + + OUTC OUTD Output + 0.6 V DAC DAC B 1 ...
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... MP7680 Rev. 3.10 Notes 12 ...