S5K433LA Samsung Semiconductor, Inc., S5K433LA Datasheet
S5K433LA
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S5K433LA Summary of contents
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... INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA (1/4” VGA CMOS Image Sensor) Preliminary Specification Revision 0.3.1 July 2002 S5K433CA, S5K433LA 1 ...
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... S5K433CA, S5K433LA DOCUMENT TITLE 1/4” Optical Size 640x480(VGA) 3.3V/2.8V CMOS Image Sensor REVISION HISTORY Revision No. History 0.0 Initial Draft 0.1 Pin description error corrected (LHOLD polarity). Timing chart added. 0.2 STRB signal polarity error corrected SFCM timing diagram corrected Operation description added. 0.3 DC timing characteristics specification changed ...
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... Fixed Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to the external devices, a camera system can be configured easily. S5K433CA is suitable for a camera system with standard 3.3V logic operation and S5K433LA is suitable for low power camera module with 2.8V power supply. FEATURES — ...
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... S5K433CA, S5K433LA BLOCK DIAGRAM Main Clock MCLK Divider RSTN STBYN Timing Generator VSYNC HSYNC DCLK Control Registers SCL Interface SDA 4 10-bit Column ADC Odd Column CDS Active Pixel Sensor Array Even Column CDS 10-bit Column ADC Figure 1. Block Diagram 1/4” VGA CMOS IMAGE SENSOR ...
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... Figure 2. Pixel Array Configuration S5K433CA, S5K433LA Optical Black Pixels ...
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... S5K433CA, S5K433LA PIN CONFIGURATION (NC) (NC) DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 (NC) (NC First Readout Pixel 17 18 Figure 3. Pin Configuration 1/4” VGA CMOS IMAGE SENSOR 42 STBYN 41 VBBA 40 VSSA 39 VDDA 38 VSSIO 37 (NC) 36 (NC) 35 VDDIO 34 VDDA 33 VSSA ...
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... Storage temperature NOTES: 1. The maximum allowed storage temperature for S5K433C(L)X01. 2. The maximum allowed storage temperature for S5K433C(L)X02 and S5K433C(L)X03. Symbol Value V -0 +0.3 (Max. 3. -20 to +60 OPR T -40 to +125 STG -40 to +85 S5K433CA, S5K433LA Unit V (1) C (2) 7 ...
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... S5K433CA, S5K433LA ELECTRICAL CHARACTERISTICS DC Characteristics (T = - 15pF Characteristics Symbol V Operating voltage DD (1) V Input voltage Input leakage IL (2) current I Input leakage current ILD (3) with pull-down V High Level Output OH (4) voltage V Low Level Output OL (5) voltage I High-Z output leakage ...
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... Symbol Condition V S5K433CA SAT S5K433LA S S5K433(C,L)X01 S5K433(C,L)X02 S5K433(C,L)X03 DARK S DSNU A PRNU VFPN HFPN S5K433CA, S5K433LA Min Typ Max 950 1000 - 850 900 - - 1500 - - 4000 - - 1500 - - 100 - 60 - ...
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... ADC resolution case. If 10-bit ADC resolution is used, the frequency should be over 12MHz. 2. The period time of main input clock, MCLK. 0.5V DD MCLK t PDMD DCLK t PDDO DATA t PDMO t PDDH HSYNC t PDMH t PDDV VSYNC t PDMV 10 = 2.55V to 3.05V for S5K433LA - Condition f Duty = 50% MCLK f - DCLK t DCLK output PDMD t DATA output PDMO t ...
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... SCL SCL, SDA SDA to SCL DS t SDA to SCL STH t - STS t - GSS C SCL, SDA PIN C SCL, SDA BUS R SCL, SDA S5K433CA, S5K433LA complete Min Typ Max - - 400 800 - - 1000 - - - - 300 300 - - 1200 - - 200 1 ...
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... S5K433CA, S5K433LA PIN DESCRIPTION Pin No I/O VDDD (24) Power Digital power supply VSSD (1) Power VDDIO (26, 35) Power I/O power supply VSSIO (47, 38) Power VDDA Power Analog power supply (4, 21, 34, 39) VSSA Power (3, 22, 33, 40) VBBA Power (2, 23, 32, 41) MCLK (46) I Master clock RSTN (43) ...
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... Row start point for window of interest wrp[8:0] = 14d(default) wrp_low wcp_high Column start point for window of interest wcp[8:0] = 14d(default) wcp_low wrd_high Row depth for window of interest wrd[8:0] = 480d(default) wrd_low wcw_high Column width for window of interest wcw[9:0] = 640d(default) wcw_low (Factory use only)) S5K433CA, S5K433LA Description 01b: DCLK=MCLK 2 (default) 13 ...
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... S5K433CA, S5K433LA Address Reset Bits (Hex) Value 0Bh 02h [4] [3] [2:0] 0Ch 0Dh [7:0] 0Dh 01h [4:0] 0Eh 06h [7:0] 0Fh 00h [5:0] 10h 00h [7:0] 11h 01h [7:0] 12h 00h [5] [4] [1:0] 13h 00h [7:0] 14h 00h [4:0] 15h 2Dh [7:0] 16h 20h [7:0] 17h 00h [5] [4] [1:0] 18h 00h [7:0] 19h 00h [5:0] 1Ah ...
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... Blue channel analog offset offsb[7:0] = 128 (default) pthresh Bad pixel threshold pthresh[6:0] = 20d (default) adcoffs ADC offset adcoffs[7: (default) - (Factory use only) - (Factory use only) p12stp (Factory use only) P12 start control S5K433CA, S5K433LA Description or all channel gain (ccsm=0) or all channel offset (ccsm=0) 15 ...
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... S5K433CA, S5K433LA Address Reset Bits (Hex) Value 28h 40h [7:5] [4:0] 29h 00h [7:0] 2Ah 00h [7:0] 2Bh 02h [5] [4] [3] [2] [1] [0] 16 Mnemonic - (Factory use only (Factory use only (Factory use only) - blank Blank register for general purpose - (Factory use only) - (Factory use only) - (Factory use only) ...
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... The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling can be done in four rates : full, 1/2, 1/3 and 1/4. The user controls the sub-sampling using the Sub-sampling Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space. 687 wcw Window Of Interest Figure 4. WOI definition. S5K433CA, S5K433LA 17 ...
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... S5K433CA, S5K433LA ...
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... Channel Gain = 128 / (128 – Programmable Gain Control Register Value[6:0 Programmable Gain Control 112 128 Figure 6. Relative Channel Gain S5K433CA, S5K433LA Programmable Gain Control 112 128 19 ...
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... S5K433CA, S5K433LA 2-4. Quadrisectional Global Gain Control The user can controls the global gain to change the gain for all color channels by the Global Gain Control Registers (sgg1, sgg2, sgg3, sgg4). The global gain control register is composed of four register groups and each register value decides the gain for each quarter section of output code level. ...
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... But it reduces the line resolution in horizontal direction. sgg1 sgg2 sgg3 255 511 767 ADC output code at 10-bit resolution Figure 9. Quadrisectional Glabal Gain Control S5K433CA, S5K433LA sgg4 sgg1=1111b sgg2=0111b sgg3=0011b sgg4=0000b sgg1=0111b sgg2=0111b sgg3=0111b sgg4=0111b ...
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... S5K433CA, S5K433LA Serial Interface 2 The industry standard serial interface. The I features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the SCL is input only ...
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... Delayed Vertical Sync Case) VSYNC vsstrt HSYNC DATA 2 rows ( Vertical Data Valid Mode Case) vsdisp=1 VSYNC HSYNC (hsdisp=0) HSYNC (hsdisp=1) DATA 1 frame = wrd + vblank ( 525 rows ) wrd (480 rows) 1 frame = wrd + vblank vswd wrd S5K433CA, S5K433LA vblank (45 rows) 2 rows vblank 23 ...
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... S5K433CA, S5K433LA HORIZONTAL TIMING DIAGRAM ( Default Case ) VSYNC HSYNC hswd 10 DCLK ( 32 DCLK) DCLK DATA ( 14th column) ( Delayed Horizontal Sync Case ) VSYNC HSYNC hsstrt DCLK DATA 42 DCLK ( Horizontal Data Valid Mode Case ) hsdisp=1 VSYNC HSYNC DCLK DATA 42 DCLK 24 1 row = wcw + hblank ( 780 columns ) ...
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... INCH VGA CMOS IMAGE SENSOR PACKAGE DIMENSION 48pin CLCC 7 TOP VIEW 18 SIDE VIEW BOTTOM VIEW R 0.15 4 Corners 14.22SQ +0.30/-0. Glass 11.176 0.13 1.016 0. 0.51 0.08 S5K433CA, S5K433LA 42 Center of Image Area (X=+0.50 0.15, Y=0.00 0.15 from package center) Max. Chip Rotation = 1.5 degree Max. Chip Tilt = 0.05mm 31 0.55 0.05 1.65 0.18 1.016 0.18 25 ...