S5K711CA Samsung Semiconductor, Inc., S5K711CA Datasheet
S5K711CA
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S5K711CA Summary of contents
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... INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA (1/7” CIF CMOS Image Sensor) Preliminary Specification Revision 0.2 Apr. 2002 S5K711CA, S5K711LA 1 ...
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... S5K711CA, S5K711LA DOCUMENT TITLE 1/7” Optical Size 352x352(CIF) 3.3V/2.8V CMOS Image Sensor REVISION HISTORY Revision No. History 0.0 Initial Draft 0.1 Pin description error corrected (LHOLD polarity). Timing chart added. 0.2 STRB signal polarity error corrected SFCM timing diagram corrected Operation description added. 2 1/7” CIF CMOS IMAGE SENSOR ...
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... Pattern Noise (FPN) drastically. With its few interface signals and 8-bit raw data directly connected to the external devices, a camera system can be configured easily. S5K711CA is suitable for a camera system with standard 3.3V logic operation and S5K711LA is suitable for low power camera module with 2.8V power supply. ...
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... S5K711CA, S5K711LA BLOCK DIAGRAM Main Clock MCLK Divider RSTN STBYN STRB Timing LHOLD Generator VSYNC HSYNC DCLK Control Registers SCL Interface SDA 4 1/7” CIF CMOS IMAGE SENSOR 8-bit Column ADC Odd Column CDS Active Pixel Sensor Array Even Column CDS ...
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... S5K711CA, S5K711LA Optical Black Pixels ...
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... S5K711CA, S5K711LA PIN CONFIGURATION DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 First Readout Pixel 12 1/7” CIF CMOS IMAGE SENSOR 28 STBYN 27 VSSA 26 VDDA 25 STRB 24 LHOLD 23 VDDA 22 VSSA 21 TEST2 ...
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... Storage temperature NOTES: 1. The maximum allowed storage temperature for S5K711C(L)X01. 2. The maximum allowed storage temperature for S5K711C(L)X02 and S5K711C(L)X03. Symbol Value V -0 +0.3 (Max. 3. -20 to +60 OPR T -40 to +125 STG -40 to +85 S5K711CA, S5K711LA Unit V (1) C (2) 7 ...
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... S5K711CA, S5K711LA ELECTRICAL CHARACTERISTICS DC Characteristics (T = - 15pF Characteristics Symbol V Operating voltage DD (1) V Input voltage Input leakage IL (2) current I Input leakage current ILD (3) with pull-down V High Level Output OH (4) voltage V Low Level Output OL (5) voltage I High-Z output leakage ...
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... Symbol Condition V S5K711CA SAT S5K711LA S S5K711(C,L)X01 S5K711(C,L)X02 S5K711(C,L)X03 DARK S/N DSNU PRNU VFPN HFPN S5K711CA, S5K711LA Min Typ Max 950 1000 - 850 900 - - 1500 - - 4000 - - 1500 - - 100 - 48 - ...
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... S5K711CA, S5K711LA AC Characteristics (V = 3.0V to 3.6V for S5K711CA Characteristic Symbol Main input clock frequency Data output clock frequency Propagation delay time from main input clock Propagation delay time from data output clock Reset input pulse width Standby input pulse width NOTES: 1. The period time of main input clock, MCLK. ...
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... Test input signal. Though it can be opened in normal operation (internally pulled down recommended to ground the test pins. Test input signal. Though it can be opened in normal operation (internally pulled down recommended to ground the test pins. S5K711CA, S5K711LA Function 10 10 ...
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... S5K711CA, S5K711LA Control Registers Address Reset Bits (Hex) Value 00h 00h [5] [4] [3] [2] [1] [0] 01h 10h [7] [6] [5:4] [3:2] [1:0] 02h 00h [0] 03h 0Eh [7:0] 04h 00h [0] 05h 0Eh [7:0] 06h 01h [0] 07h 20h [7:0] 08h 01h [1:0] 09h 60h [7:0] 0Ah 80h [7:0] 12 Mnemonic sckinv (Factory use only) Column color inversion ...
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... HSYNC width hswd[7:0] = 32d (default) hspolar HSYNC polarity 0: active high (default), 1: active low hsdisp HSYNC display mode 0: sync mode (default), 1: data valid mode hsstart_high HSYNC start position hsstrt[9: (default) hsstart_low hblank_high Horizontal blank depth hblank[13:0] = 148d (default) hblank_low S5K711CA, S5K711LA Description 13 ...
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... S5K711CA, S5K711LA Address Reset Bits (Hex) Value 1Bh 77h [3:0] [7:4] 1Ch 77h [3:0] [7:4] 1Dh 00h [6:0] 1Eh 00h [6:0] 1Fh 00h [6:0] 20h 00h [6:0] 21h 80h [7:0] 22h 80h [7:0] 23h 80h [7:0] 24h 80h [7:0] 25h 14h [6:0] 26h 00h [7:0] 27h 01h [4] [3:0] 14 Mnemonic st sgg1 1 sectional global gain sgg1[3: (default) ...
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... Reset start control blank Blank register for general purpose vtest (Factory use only) Vertical function test mode htest (Factory use only) Horizontal function test mode i2ctest (Factory use only) IIC test mode nandtree (Factory use only) NAND tree test mode S5K711CA, S5K711LA Description 15 ...
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... S5K711CA, S5K711LA OPERATION DESCRIPTION 1. Output Data Format 1-1. Main Clock Divider All the data output and sync signals are synchronized to data clock output (DCLK generated by dividing the input main clock (MCLK). The dividing ratio and 8 according to main clock dividing control register (mcdiv) ...
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... S5K711CA, S5K711LA ...
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... S5K711CA, S5K711LA 2. Analog to Digital Converter ( ADC) The image sensor has on-chip ADC. Two-channel column parallel ADC scheme is used for separated color channel gain and offset control. 2-1. ADC resolution The ADC resolution is fixed to 8bit. 2-2. Correlated Double Sampling ( CDS ) The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action and some fixed pattern noise by the in-pixel amplifier offset deviation ...
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... Figure 7. Relative Global Gain MCLK frequency (MHz) S5K711CA, S5K711LA ...
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... S5K711CA, S5K711LA Figure 8. Recommended Minimum Global Gain Control Value By appropriately programming these four register values, the different output resolution according to the signal can be achieved and the intra-scene dynamic range can be increased by 16 times. In another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curve as shown in Figure 9 ...
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... C Bus Write Cycle D7 “0” “0” “1” Write Ack D7 “0” “0” “1” Read Ack 2 Figure 11 Bus Read Cycle S5K711CA, S5K711LA 2 C bus interface is composed of following I2C Register Address I2C Register Address ...
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... S5K711CA, S5K711LA TIMING CHART VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode ( Default Case ) VSYNC vswd (1row) rows HSYNC DATA wrp (14th row) ( Delayed Vertical Sync Case) VSYNC vsstrt HSYNC DATA 2 rows ( Vertical Data Valid Mode Case) vsdisp=1 VSYNC HSYNC (hsdisp=0) HSYNC ...
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... Integration time for 1st readout row Integration time for 2nd readout row 1 row 1 row 1 row sint X (1 row time) VSYNC HSYNC DATA Normal frame output Integration time for 3rd readout row Integration time for 4th readout row 2 rows S5K711CA, S5K711LA 23 ...
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... S5K711CA, S5K711LA HORIZONTAL TIMING DIAGRAM ( Default Case ) VSYNC HSYNC hswd 10 DCLK ( 32 DCLK) DCLK DATA ( 14th column) ( Delayed Horizontal Sync Case ) VSYNC HSYNC hsstrt DCLK DATA 42 DCLK ( Horizontal Data Valid Mode Case ) hsdisp=1 VSYNC HSYNC DCLK DATA 42 DCLK 24 1 row = wcw + hblank ( 500 columns ) ...
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... INCH CIF CMOS IMAGE SENSOR LINE HOLD MODE TIMING DIAGRAM LHOLD HSYNC (i)-th row DATA line held (i+1)-th row hblank – 42 DCLK S5K711CA, S5K711LA (i+2)-th row 42 DCLK hblank 25 ...
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... S5K711CA, S5K711LA PACKAGE DIMENSION 32pin CLCC TOP VIEW SIDE VIEW 1.016 BOTTOM VIEW R 0.15 4 Corners 26 10.668SQ +0.25/-0. Glass 7.112 0.13 0. 0.51 0.08 1/7” CIF CMOS IMAGE SENSOR 28 Center of Image Area (X=+0.48 0.15, Y=0.00 0.15 from package center) Max. Chip Rotation = 1.5 degree 21 Max. Chip Tilt = 0.05mm ...