DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 45
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DSP56721
Manufacturer Part Number
DSP56721
Description
Dsp56721 Multi-core Audio Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56721.pdf
(56 pages)
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LCLK cycle time
Input setup to LCLK (except LGTA/LUPWAIT)
Input hold from LCLK (except LGTA/LUPWAIT)
LGTA valid time
LUPWAIT valid time
LALE negedge to LAD (address phase) invalid (address latch hold time)
LALE valid time
Output setup from LCLK (except LAD[23:0] and LALE)
Output hold from LCLK (except LAD[23:0] and LALE)
LAD[23:0] output setup from LCLK
LAD[23:0] output hold from LCLK
LCLK to output high impedance for LAD[23:0]
Notes:
1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
Freescale Semiconductor
Table 21. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Symphony
Parameter
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
1
Symbol
T
T
T
T
T
T
T
T
T
T
T
upwait
T
ale_h
out_s
out_h
ad_s
ad_h
ad_z
in_s
in_h
gta
ale
clk
Min
20
22
22
14
—
-1
8
4
9
8
8
7
Max
—
—
—
—
—
—
—
—
—
—
—
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
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