DSPIC30F6015 Microchip Technology Inc., DSPIC30F6015 Datasheet - Page 229

• Manufacturer Part Number: DSPIC30F6015
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

Instruction Set
Internet Address ............................................................... 231
Interrupt Controller
Interrupt Priority ................................................................. 40
Interrupt Sequence ............................................................ 43
Interrupts ............................................................................ 39
I
I
I
I
I
M
Memory Organization ......................................................... 21
Microchip Internet Web Site ............................................. 231
Migration from dsPIC30F6010 to dsPIC30F6010A .......... 223
Modulo Addressing ............................................................ 34
Motor Control PWM Module ............................................... 93
MPLAB ASM30 Assembler, Linker, Librarian .................. 172
MPLAB ICD 2 In-Circuit Debugger .................................. 173
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment Software . 171
MPLAB PM3 Device Programmer ................................... 173
MPLINK Object Linker/MPLIB Object Librarian ............... 172
© 2007 Microchip Technology Inc.
2
2
2
2
2
C Master Operation
C Module
C 10-bit Slave Mode Operation ..................................... 109
C 7-bit Slave Mode Operation ....................................... 109
C™ Module ................................................................... 107
Overview .................................................................. 166
Summary .................................................................. 163
Register Map (dsPIC30F6010A) ................................ 44
Register Map (dsPIC30F6015) .................................. 45
Interrupt Stack Frame ................................................ 43
Baud Rate Generator ............................................... 111
Clock Arbitration ....................................................... 112
Multi-Master Communication, Bus Collision
Reception ................................................................. 111
Transmission ............................................................ 111
Addresses ................................................................ 109
General Call Address Support ................................. 111
Interrupts .................................................................. 111
IPMI Support ............................................................ 111
Master Operation ..................................................... 111
Master Support ........................................................ 111
Operating Function Description ............................... 107
Operation During CPU Sleep and Idle Modes ......... 112
Pin Configuration ..................................................... 107
Programmer’s Model ................................................ 107
Register Map ............................................................ 113
Registers .................................................................. 107
Slope Control ........................................................... 111
Software Controlled Clock Stretching (STREN = 1) . 110
Various Modes ......................................................... 107
10-bit Mode Slave Reception ................................... 110
10-bit Mode Slave Transmission .............................. 110
Reception ................................................................. 109
Transmission ............................................................ 109
Core Register Map ..................................................... 30
Applicability ................................................................ 36
Operation Example .................................................... 35
Start and End Address ............................................... 35
W Address Register Selection ................................... 35
8-Output Register Map ............................................. 102
In-Circuit Emulator ................................................... 173
In-Circuit Emulator ................................................... 173
and Bus Arbitration .......................................... 112
dsPIC30F6010A/6015
O
Operating Current (I
Oscillator
Oscillator Configurations .................................................. 150
Oscillator Selection .......................................................... 147
Output Compare Module ................................................... 83
P
Packaging Information ..................................................... 215
Peripheral Module Disable (PMD) Registers ................... 160
PICSTART Plus Development Programmer .................... 174
Pin Diagrams ................................................................... 3–4
Pinout Descriptions ............................................................ 10
POR. See Power-on Reset.
Position Measurement Mode ............................................. 88
Power Saving Modes
Power-on Reset (POR) .................................................... 147
Power-Saving Modes ....................................................... 158
Power-Saving Modes (Sleep and Idle) ............................ 147
Program Address Space .................................................... 21
Program Counter ............................................................... 14
Program Data Table Access .............................................. 24
Program Space Visibility
Programmable ................................................................. 147
Programmable Digital Noise Filters ................................... 89
Programmer’s Model ......................................................... 14
Programming Operations ................................................... 49
Protection Against Accidental Writes to OSCCON .......... 153
PWM Duty Cycle Comparison Units .................................. 97
Operating Modes (Table) ......................................... 148
System Overview ..................................................... 147
Fail-Safe Clock Monitor ........................................... 152
Fast RC (FRC) ......................................................... 151
Initial Clock Source Selection .................................. 150
Low-Power RC (LPRC) ........................................... 152
LP Oscillator Control ................................................ 151
Phase Locked Loop (PLL) ....................................... 151
Start-up Timer (OST) ............................................... 151
Interrupts ................................................................... 85
Operation During CPU Idle Mode .............................. 85
Operation During CPU Sleep Mode .......................... 85
Register Map ............................................................. 86
Marking .................................................................... 215
Idle ........................................................................... 159
Sleep ....................................................................... 158
Oscillator Start-up Timer (OST) ............................... 147
Power-up Timer (PWRT) ......................................... 147
Construction .............................................................. 22
Data Access from Program Memory Using
Data Access from, Address Generation .................... 22
Memory Map .............................................................. 21
Table Instructions
Window into Program Space Operation .................... 25
Diagram ..................................................................... 15
Algorithm for Program Flash ...................................... 49
Erasing a Row of Program Memory .......................... 49
Initiating the Programming Sequence ....................... 50
Loading Write Latches ............................................... 50
Duty Cycle Immediate Updates ................................. 97
Duty Cycle Register Buffers ...................................... 97
Table Instructions .............................................. 23
TBLRDH ............................................................ 23
TBLRDL ............................................................. 23
TBLWTH ............................................................ 23
TBLWTL ............................................................ 23
DD
) ................................................... 178
DS70150C-page 227