DSPIC33FJ32MC202 Microchip Technology Inc., DSPIC33FJ32MC202 Datasheet - Page 221
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DSPIC33FJ32MC202
Manufacturer Part Number
DSPIC33FJ32MC202
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ32MC202.pdf
(292 pages)
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TABLE 20-2:
© 2007 Microchip Technology Inc.
WDTPOST<3:0>
POSCMD<1:0>
FNOSC<2:0>
FCKSM<1:0>
OSCIOFNC
IOL1WAY
WDTPRE
FWDTEN
PWMPIN
Bit Field
WINDIS
DSPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
FOSCSEL
Register
FOSC
FOSC
FOSC
FWDT
FWDT
FWDT
FWDT
FOSC
FPOR
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) oscillator with postscaler
110 = Internal Fast RC (FRC) oscillator with divide-by-16
101 = LPRC oscillator
100 = Secondary (LP) oscillator
011 = Primary (XT, HS, EC) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRC) oscillator with PLL
000 = FRC oscillator
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Peripheral pin select configuration
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
0001 = 1:2
0000 = 1:1
Motor Control PWM Module Pin Mode bit
1 = PWM module pins controlled by PORT register at device Reset
0 = PWM module pins controlled by PWM module at device Reset
.
.
.
Clearing the SWDTEN bit in the RCON register will have no effect.)
disabled by clearing the SWDTEN bit in the RCON register)
(tri-stated)
(configured as output pins)
Preliminary
Description
DS70283B-page 219
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