DSPIC33FJ12GP202 Microchip Technology Inc., DSPIC33FJ12GP202 Datasheet - Page 92
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DSPIC33FJ12GP202
Manufacturer Part Number
DSPIC33FJ12GP202
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ12GP202.pdf
(242 pages)
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dsPIC33FJ12GP201/202
REGISTER 7-1:
DS70264B-page 90
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
CLKLOCK
R/W-0
U-0
—
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Selection bits (read-only)
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator (FRC) with PLL
010 = Primary oscillator (XT, HS, EC)
011 = Primary oscillator (XT, HS, EC) with PLL
100 = Secondary oscillator (SOSC)
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC oscillator (FRC) with Divide-by-16
111 = Fast RC oscillator (FRC) with Divide-by-n
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator (FRC) with PLL
010 = Primary oscillator (XT, HS, EC)
011 = Primary oscillator (XT, HS, EC) with PLL
100 = Secondary oscillator (SOSC)
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC oscillator (FRC) with Divide-by-16
111 = Fast RC oscillator (FRC) with Divide-by-n
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled (FOSC<FCKSM> = 0b01)
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
IOLOCK: Peripheral Pin Select Lock bit
1 = Peripherial Pin Select is locked, write to peripheral pin select register is not allowed
0 = Peripherial Pin Select is unlocked, write to peripheral pin select register is allowed
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
Unimplemented: Read as ‘0’
IOLOCK
R/W-0
R-0
OSCCON: OSCILLATOR CONTROL REGISTER
COSC<2:0>
y = Value set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
LOCK
R-0
R-0
R-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-0
U-0
CF
—
R/W-y
U-0
—
© 2007 Microchip Technology Inc.
NOSC<2:0>
x = Bit is unknown
LPOSCEN
R/W-0
R/W-y
OSWEN
R/W-y
R/W-0
bit 8
bit 0
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