87C52 NXP Semiconductors, 87C52 Datasheet
87C52
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87C52 Summary of contents
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... K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM Product specification Replaces datasheet 80C51/87C51/80C31 of 2000 Jan 20 hilips Semiconductors INTEGRATED CIRCUITS 2000 Aug 07 ...
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... K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM DESCRIPTION The Philips 80C51/87C51/80C52/87C52 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2 5.5 V. The 8xC51 and 8xC52 contain a 128 ...
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... Plastic Leaded Chip Carrier TEMPERATURE RANGE ( MHz + MHz + MHz F = – + MHz F = – + Product specification 80C51/87C51/80C52/87C52 VOLTAGE FREQ. DWG. # RANGE (MHz 2 5 SOT129-1 SOT129 1 2 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM 80C52/87C52 ORDERING INFORMATION MEMORY SIZE 8K 8 ROM P80C52SBPN OTP P87C52SBPN ROM P80C52SBAA OTP P87C52SBAA ROM P80C52SBBB OTP P87C52SBBB ROM P80C52SFP N –40 to +85, Plastic Dual In-line Package ...
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... V SS RAM ADDR RAM REGISTER B ACC REGISTER PSEN ALE/PROG TIMING AND EAV PP CONTROL RST PD OSCILLATOR XTAL1 XTAL2 2000 Aug 07 80C51/87C51/80C52/87C52 P0.0–P0.7 P2.0–P2.7 PORT 0 PORT 2 DRIVERS DRIVERS PORT 0 PORT 2 LATCH LATCH STACK POINTER TMP1 TMP2 ALU SFRs TIMERS PSW PORT 1 PORT 3 LATCH ...
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... PIN FUNCTIONS PP Pin Function 1 P1.5 2 P1.6 3 P1.7 4 RST 5 P3.0/RxD 6 NIC* 7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD 14 XTAL2 15 XTAL1 * NO INTERNAL CONNECTION 6 Product specification 80C51/87C51/80C52/87C52 LCC Pin Function Pin Function 16 P3.4/T0 31 P2.7/A15 32 PSEN 17 P3.5/T1 33 ALE 18 P3.6/WR 34 NIC* 19 P3.7/RD 20 XTAL2 35 EA P0.7/AD7 ...
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... NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V 2000 Aug 07 80C51/87C51/80C52/87C52 Ground reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM Table 1. 80C51/87C51/80C52/87C52 Special Function Registers DIRECT SYMBOL DESCRIPTION ADDRESS ACC* Accumulator E0H AUXR# Auxiliary 8EH AUXR1# Auxiliary 1 A2H B* B register F0H DPTR: Data Pointer (2 bytes) ...
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... Internal Power-down External 2000 Aug 07 80C51/87C51/80C52/87C52 the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. WUPD (AUXR1.3–Wakeup from Power Down) enables or disables the wakeup from power down with external interrupt. ...
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... 2000 Aug 07 80C51/87C51/80C52/87C52 TH2 captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt) ...
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... OSC Pin Transition Detector T2EX Pin EXEN2 2000 Aug 07 RCLK TCLK EXEN2 TR2 TL2 TH2 (8-bits) (8-bits) Control TR2 Capture RCAP2L RCAP2H Control Figure 2. Timer 2 in Capture Mode 11 Product specification 80C51/87C51/80C52/87C52 (LSB) C/T2 CP/RL2 SU00728 TF2 Timer 2 Interrupt EXF2 SU00066 ...
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... EXEN2 Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) 2000 Aug 07 — — — — TL2 TH2 (8-BITS) (8-BITS) CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL 12 Product specification 80C51/87C51/80C52/87C52 Reset Value = XXXX XX00B T2OE DCEN 1 0 SU00729 TF2 TIMER 2 INTERRUPT EXF2 SU00067 ...
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... TL2 TH2 (8-bits) (8-bits) Control TR2 Reload RCAP2L RCAP2H Timer 2 EXF2 Interrupt Control Figure 6. Timer 2 in Baud Rate Generator Mode 13 Product specification 80C51/87C51/80C52/87C52 TOGGLE EXF2 TF2 INTERRUPT COUNT DIRECTION DOWN T2EX PIN SU00730 Timer 1 Overflow 2 “0” “1” SMOD “ ...
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... TH2 and TL2 baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; 2000 Aug 07 80C51/87C51/80C52/87C52 under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors ...
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... Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the 2000 Aug 07 80C51/87C51/80C52/87C52 T2CON INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 00H ...
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... OSC 2000 Aug 07 80C51/87C51/80C52/87C52 Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature ...
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... POF GF1 GF0 Figure 8. UART Framing Error Detection SM0 SM1 SM2 REN COMPARATOR 17 Product specification 80C51/87C51/80C52/87C52 D7 D8 ONLY IN STOP MODE 2, 3 BIT SCON TI RI (98H) PCON PD IDL (87H) SU01191 D7 D8 SCON TB8 RB8 TI RI (98H) ...
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... K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM Interrupt Priority Structure The 80C51/87C51 and 80C52/87C52 have a 6-source four-level interrupt structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register that makes the four-level interrupt structure possible ...
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... Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. 2000 Aug PT2 PS PT1 PX1 Figure 11. IP Registers PT2H PSH PT1H PX1H Figure 12. IPH Registers 19 Product specification 80C51/87C51/80C52/87C52 1 0 PT0 PX0 SU00572 1 0 PT0H PX0H SU01058 ...
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... JMP @ A + DPTR The data pointer can be accessed on a byte-by-byte basis by DPS specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details Product specification 80C51/87C51/80C52/87C52 DPTR1 DPTR0 DPH DPL (83H) (82H) EXTERNAL DATA ...
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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted. AC ELECTRICAL CHARACTERISTICS + – +85 C amb SYMBOL FIGURE 1/t 29 Oscillator frequency CLCL 2000 Aug 07 80C51/87C51/80C52/87C52 PARAMETER Speed versions : S (16 MHz) U (33 MHz) 21 Product specification RATING UNIT 0 to +70 or –40 to +85 C –65 to +150 +13.0 V – ...
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... amb T = – +85 C amb on ALE and PSEN to momentarily fall below the – + –750 A. amb TL must be externally limited as follows the voltage specification Product specification 80C51/87C51/80C52/87C52 LIMITS UNIT UNIT 1 MIN TYP MAX –0.5 0.2 V –0 –0.5 0 ...
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... amb T = – +85 C amb on ALE and PSEN to momentarily fall below the – + –750 A. amb TL must be externally limited as follows the voltage specification Product specification 80C51/87C51/80C52/87C52 LIMITS UNIT UNIT 1 MIN TYP MAX –0.5 0.2 V –0 +0.9 V +0.5 V ...
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... Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the 87C51, 80C51, 87C52, or 80C52 to devices with float times permitted. This limited bus contention will not cause damage to Port 0 drivers. ...
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... Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. ...
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... RHDX DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPF Figure 15. External Data Memory Read Cycle 26 Product specification 80C51/87C51/80C52/87C52 = Time for address valid to ALE low. =Time for ALE low to PSEN low. A0–A7 A8–A15 SU00006 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH ...
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... Figure 17. Shift Register Mode Timing –0.5 0.7V CC 0.2V –0 CHCX CHCL CLCX CLCH t CLCL Figure 18. External Clock Drive 27 Product specification 80C51/87C51/80C52/87C52 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH SU00026 SET TI VALID VALID VALID VALID SET RI SU00027 SU00009 ...
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... V IH Figure 19. AC Testing Input/Output Valid only within frequency specifications of the device under test 2000 Aug 07 80C51/87C51/80C52/87C52 V +0.1V LOAD V LOAD V –0.1V LOAD NOTE: For timing purposes, a port is no longer floating when a 100mV change from max for a logic ‘0’. ...
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... CLCH CHCL RST P0 EA (NC) XTAL2 XTAL1 V SS SU00016 Test Condition, Power Down Mode 5 Product specification 80C51/87C51/80C52/87C52 RST XTAL2 XTAL1 V SS SU00720 Test Condition, Idle Mode CC All other pins are disconnected SU00009 ...
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... ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while V 12.75 V. Each programming pulse is low for 100 and high for a minimum Trademark phrase of Intel Corporation. 2000 Aug 07 80C51/87C51/80C52/87C52 device. The V source should be well regulated and free of glitches PP and overshoot ...
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... NOTES – programmed. U – unprogrammed. 2. Any other combination of the security bits is not defined. A0– 4–6MHz 5 PULSES ALE/PROG: SEE EXPLODED VIEW BELOW 1 0 ALE/PROG: 2000 Aug 07 80C51/87C51/80C52/87C52 RST EA/V PP P3.6 ALE/PROG P3.7 EPROM/OTP PSEN XTAL2 P2.7 P2.6 XTAL1 P2.0–P2 Figure 26 ...
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... PROG GHSL PP t PROG width GLGH t Address to data valid AVQV t ENABLE low to data valid ELQZ t Data float after ENABLE EHQZ t PROG high to PROG low GHGL NOTE: 1. Not tested. 2000 Aug 07 80C51/87C51/80C52/87C52 + RST EA/V PP P3.6 ALE/PROG P3.7 EPROM/OTP PSEN XTAL2 P2.7 P2.6 XTAL1 P2.0–P2 Figure 28 ...
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... EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). 33 Product specification 80C51/87C51/80C52/87C52 * VERIFICATION ADDRESS t AVQV DATA OUT ...
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... If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Enabled Security Bit #2: Enabled Encryption: No 2000 Aug 07 80C51/87C51/80C52/87C52 BIT(S) 7:0 7 Disabled Disabled Yes If Yes, must send key file ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM DIP40: plastic dual in-line package; 40 leads (600 mil) 2000 Aug 07 80C51/87C51/80C52/87C52 35 Product specification SOT129-1 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM PLCC44: plastic leaded chip carrier; 44 leads 2000 Aug 07 80C51/87C51/80C52/87C52 36 Product specification SOT187-2 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 2000 Aug 07 80C51/87C51/80C52/87C52 37 Product specification SOT307-2 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Aug 07 80C51/87C51/80C52/87C52 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 38 Product specification All rights reserved. Printed in U.S.A. Date of release: 08-00 9397 750 07404 ...