HT36A1 Holtek Semiconductor Inc., HT36A1 Datasheet - Page 10

• Manufacturer Part Number: HT36A1
• Description: Ht36a1 -- Music Synthesizer 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

The internal Timer Counter 0 interrupt is initialized by set-
ting the Timer Counter 0 interrupt request flag (T0F; bit 5
of INTC), caused by a Timer Counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The Timer Counter 1 interrupt is operated in the same
manner as Timer Counter 0. The related interrupt con-
trol bits ET1I and T1F of the Timer Counter 1 are bit 3
and bit 6 of the INTC respectively.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the RET or RETI in-
struction may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.
The EMI, ET0I, ET1I are used to control the en-
abling/disabling of interrupts. These bits prevent the re-
quested interrupt from being serviced. Once the
interrupt request flags (T0F, T1F) are set, they will re-
main in the INTC register until the interrupts are ser-
viced or cleared by a software instruction.
Rev. 1.10
Timer Counter 0 overflow
Timer Counter 1 overflow
Bit No.
0
1
2
3
4
5
6
7
Interrupt Source
Label
ET0I
ET1I
EMI
T0F
T1F
Controls the Master (Global) interrupt (1=enabled; 0=disabled)
Unused bit, read as 0
Controls the Timer Counter 0 interrupt (1=enabled; 0=disabled)
Controls the Timer Counter 1 interrupt (1=enabled; 0=disabled)
Unused bit, read as 0
Internal Timer Counter 0 request flag (1=active; 0=inactive)
Internal Timer Counter 1 request flag (1=active; 0=inactive)
Unused bit, read as 0
Priority
1
2
Vector
0CH
08H
INTC (0BH) Register
10
It is recommended that a program does not use the
cause interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applica-
tions, if only one stack is left and enabling the interrupt is
not well controlled, once the CALL subroutine operates
in the interrupt subroutine, it may damage the original
control sequence.
Oscillator Configuration
The HT36A1 provides two types of oscillator circuit for
the system clock, i.e., RC oscillator and crystal oscilla-
tor. No matter what type of oscillator, the signal divided
by 2 is used for the system clock (f
HALT mode stops the system oscillator and ignores ex-
ternal signal to conserve power. If the RC oscillator is
used, an external resistor between OSC1 and VSS is re-
quired, and the range of the resistance should be from
30k to 680k . The system clock, divided by 4 (f
f
sistor, which can be used to synchronize external logic.
The RC oscillator provides the most cost effective solu-
tion. However, the frequency of the oscillation may vary
with VDD, temperature, and the chip itself due to pro-
cess variations. It is therefore, not suitable for timing
sensitive operations where accurate oscillator fre-
quency is desired.
SYS
CALL subroutine within the interrupt subroutine. Be-
/4=f
Function
OSC
/8), is available on OSC2 with pull-high re-
System Oscillator
SYS
March 12, 2007
=f
HT36A1
OSC
/2). The
OSC2
=