RS5C348A RICOH Co.,Ltd., RS5C348A Datasheet - Page 36

• Manufacturer Part Number: RS5C348A
• Description: 4-wire Serial Interface Real-time Clock
• Manufacturer: RICOH Co.,Ltd.

Rx5C348A/B
Rev.2.01
32-kHz CLOCK OUTPUT
12345
*2) Level Mode:
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ± 3.784ms. For
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ± 3.784 ms.
For the Rx5C348A, 32.768-kHz clock pulses are output from the 32KOUT pin when either the /CLEN1 bit in
the Control Register 2 or the /CLEN2 bit in the Control Register 1 is set to 0. When both the /CLEN1 and
/CLEN2 bits are set to 0, the 32KOUT pin output is driven high (off).
The 32KOUT pin output is synchronized with the /CLEN1 and /CLEN2 bit settings as illustrated in the timing
chart below.
For the Rx5C348B, 32.768-kHz clock pulses are output from the 32KOUT pin regardless of such internal
register settings.
32KOUT PIN
In the pulse mode, the increment of the second counter is delayed by approximately 92 µ s from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock
pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the
/INTR pin low.
Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1
hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1
second are output in synchronization with the increment of the second counter as illustrated in the
timing chart below.
follows:
example, 1-Hz clock pulses will have a duty cycle of 50 ± 0.3784%.
/CLEN1or2
/CLEN1
(D3 at Address Fh)
/INTR Pin
CTFG Bit
1
0(Default)
*
Max.62.0µs
(Increment of
second counter)
Setting CTFG bit to 0
/CLEN2
(D4 at Address Eh)
1
*
0(Default)
(Increment of
second counter)
32KOUT PIN
(N-channel Open Drain)
OFF(H)
Clock pulses
- 36 -
(Increment of
second counter)
Setting CTFG bit to 0