MC56U032NCFA Samsung Semiconductor, Inc., MC56U032NCFA Datasheet - Page 44

• Manufacturer Part Number: MC56U032NCFA
• Description: Flash Card
• Manufacturer: Samsung Semiconductor, Inc.

8
7:6
5
4
3:2
1:0
4.9.8 Command Response Timings
All timing diagrams use the following schematics and abbreviations:
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
R
Timing Values
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :
MultiMediaCard
CMD
EADY_FOR_DATA
reserved
APP_CMD
reserved
reserved for application specific commands
reserved for manufacturer test mode
respectively R
S
T
P
E
Z
D
*
CRC
NCR
NID
NAC
NRC
NCC
NWR
NST
DAT
. Actively driven P-bits are less sensitive to noise superposition.
TM
Start bit (= ‘0’)
Transmitter bit (Host = ‘1’, Card = ‘0’)
One-cycle pull-up (= ‘1’)
End bit (=1)
High impedance state (-> = ‘1’)
Data bits
Repetition
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
SX
SR
Min
2
5
2
8
8
2
2
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9–15 = reserved
‘0’ = not ready
‘1’ = ready
Permanently 0
‘0’ = disabled
‘1’ = enabled
Permanently 0
Max
64
5
10*(TAAC*Fop+1
00*NSAC)
--
--
--
2
corresponds to buffer empty signaling on
The card will expect ACMD or indication
the bus
that the command has been interpreted
as ACMD.
Unit
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
A
C
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