MC56F8347 Freescale Semiconductor, Inc, MC56F8347 Datasheet
MC56F8347
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MC56F8347 Summary of contents
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... Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8347 Rev.11 01/2007 freescale.com ...
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Version History Rev 0 Initial release Rev 1.0 Fixed typos in Section 1.1.3, Replace any reference to Flash Interface Unit with Flash Module, corrected pin number for D14 in thermal numbers for 160 LQFP in corrected temperature range in and ...
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General Description Note: Features in italics are NOT available in the 56F8147 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 4MB of off-chip ...
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Part 1: Overview 1.1. 56F8347/56F8147 Features . . . . . . . . . . . ...
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Part 1 Overview 1.1 56F8347/56F8147 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) ...
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Memory Note: Features in italics are NOT available in the 56F8147 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...
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Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8347, SPI1 can also ...
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Features The 56F8347 controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. It also supports program execution from external memory. ...
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Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the ...
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Architecture Block Diagram Note: Features in italics are NOT available in the 56F8147 device and are shaded in the following figures. The 56F8347/56F8147 architecture is shown in 56800E system buses communicate with internal memories, the external memory interface and ...
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CHIP TAP Controller TAP Linking Module External JTAG Port NOT available on the 56F8147 device. Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the I/O to the FM over the peripheral ...
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CLKGEN (OSC/PLL) Timer A 4 Quadrature Decoder 0 4 Timer D Timer B 4 Quadrature Decoder NOT available on the 56F8147 device. 12 To/From IPBus Bridge SPI 1 GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF SPI0 SCI0 ...
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Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
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... Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 14 Freescale Literature Distribution Table 1-3 Chip Documentation Description Logic State Signal State True False True False 56F8347 Technical Data, Rev.11 Centers, or online Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM MC56F8347 MC56F8347E MC56F8147E 1 Voltage Asserted Deasserted Asserted Deasserted V /V ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8347 and 56F8147 are organized into functional groups, as detailed in Table 2-1 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...
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V Power V DDA_OSC_PLL Power V DDA_ADC Power Ground V SSA_ADC Ground OCR_DIS * Other CAP Supply V 1 & Ports CLKMODE PLL and Clock (GPIOA8 - 13 (GPIOE2 ...
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Power Power V Power DDA_OSC_PLL Ground Ground Other *V CAP Supply V PP Ports CLKMODE PLL and Clock (GPIOA8 - 13 (GPIOE2 - A15 (GPIOA0 - 7) External Address GPIOB0 - ...
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Signal Pins After reset, all pins are by default the primary function. Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8147 device. If the “State During Reset” lists more than one state ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No K11 G11 125 J11 SS V ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. XTAL 93 K12 CLKO 154 C3 (GPIOA8 (GPIOA9 (GPIOA10 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No (GPIOE2 (GPIOE3 (GPIOA0 (GPIOA1) A10 21 H2 (GPIOA2) A11 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. GPIOB0 33 L1 (A16) GPIOB1 34 L3 (A17) GPIOB2 35 L2 (A18) GPIOB3 36 M1 (A19) GPIOB4 37 M2 (A20) (prescaler_ ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No P10 (GPIOF9 N10 (GPIOF10 P14 (GPIOF11 L13 (GPIOF12 L14 (GPIOF13) D5 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No (GPIOF0 (GPIOF1 (GPIOF2) D10 32 K4 (GPIOF3) D11 149 A5 (GPIOF4) D12 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No (CS0) (GPIOD8 (CS1) (GPIOD9) Freescale Semiconductor Preliminary State Type During Reset Output ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. GPIOD0 55 P6 (CS2) GPIOD1 56 L6 (CS3) GPIOD2 57 K6 (CS4) GPIOD3 58 N7 (CS5) GPIOD4 59 P7 (CS6) GPIOD5 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. TXD1 49 P4 (GPIOD6) RXD1 50 N5 (GPIOD7) TCK 137 D8 TMS 138 A8 TDI 139 B8 TDO 140 D7 Freescale ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. TRST 136 D9 PHASEA0 155 A2 (TA0) (GPIOC4) PHASEB0 156 B4 (TA1) (GPIOC5) 28 State Type During Reset Schmitt Input, Test ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. INDEX0 157 A1 (TA2) (GPOPC6) HOME0 158 B3 (TA3) (GPIOC7) SCLK0 146 A6 (GPIOE4) Freescale Semiconductor Preliminary State Type During Reset ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. MOSI0 148 B6 (GPIOE5) MISO0 147 D4 (GPIOE6) SS0 145 D5 (GPIOE7) 30 State Type During Reset Input/ In reset, SPI ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. PHASEA1 6 C1 (TB0) (SCLK1) (GPIOC0) PHASEB1 7 D1 (TB1) (MOSI1) (GPIOC1) Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. INDEX1 8 E2 (TB2) (MISO1) (GPIOC2) HOME1 9 E1 (TB3) (SS1) (GPIOC3) 32 State Type During Reset Schmitt Input, Index1 — ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. PWMA0 73 M11 PWMA1 75 P12 PWMA2 76 N11 PWMA3 78 M12 PWMA4 79 P13 PWMA5 81 N12 ISA0 126 A11 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. ISB0 61 N8 (GPIOD10) ISB1 63 L8 (GPIOD11) ISB2 64 P8 (GPIOD12) FAULTB0 67 N9 FAULTB1 68 L9 FAULTB2 69 L10 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. ANB0 116 C13 ANB1 117 B14 ANB2 118 C12 ANB3 119 B13 ANB4 120 A14 ANB5 121 A13 ANB6 122 B12 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. TD0 129 B10 (GPIOE10) TD1 130 A10 (GPIOE11) TD2 131 D10 (GPIOE12) TD3 132 E10 (GPIOE13) IRQA 65 K9 IRQB 66 ...
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Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued) Pin Ball Signal Name No. No. EXTBOOT 124 B11 EMI_MODE 159 B2 Freescale Semiconductor Preliminary State Type During Reset Schmitt Input, External Boot — This input is ...
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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...
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The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal ...
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External Clock Source The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set the OCCS_COHL bit high as well. XTAL ...
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Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in map configurations that are possible at reset. After reset, ...
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Table 4-4 Program Memory Map at Reset Mode 0 ( Begin/End Internal Boot Address Internal Boot 16-Bit External Address Bus P:$1F FFFF External Program Memory P:$10 0000 P:$0F FFFF P:$03 0000 P:$02 FFFF P:$02 F800 P:$02 F7FF P:$02 ...
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Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8147 device. Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level core 2 3 core 3 3 core 4 3 core ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level GPIOD 32 0-2 GPIOC 33 0-2 GPIOB 34 0-2 GPIOA 35 0-2 SPI1 38 0-2 SPI1 39 0-2 SPI0 40 0-2 SPI0 41 0-2 SCI1 42 0-2 SCI1 43 ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level SCI0 68 0-2 SCI0 69 0-2 SCI0 71 0-2 SCI0 72 0-2 ADCB 73 0-2 ADCA 74 0-2 ADCB 75 0-2 ADCA 76 0-2 PWMB 77 0-2 PWMA 78 ...
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Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by ...
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EOnCE Memory Map Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — X:$FF FF92 OBAR2 (32 bits) X:$FF FF93 — X:$FF FF94 OBAR1 (24 bits) X:$FF FF95 — X:$FF FF96 OBCR ...
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Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be ...
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Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral GPIO Port F SIM Power Supervisor FM FlexCAN Table 4-10 External Memory Integration Registers Address Map Register Acronym Address Offset CSBAR 0 $0 CSBAR 1 $1 CSBAR 2 $2 ...
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Table 4-10 External Memory Integration Registers Address Map (Continued) Register Acronym Address Offset CSOR 4 $C CSOR 5 $D CSOR 6 $E CSOR 7 $F CSTC 0 $10 CSTC 1 $11 CSTC 2 $12 CSTC 3 $13 CSTC 4 $14 ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSC ...
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Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8147 device Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP TMRB0_LOAD TMRB0_HOLD TMRB0_CNTR TMRB0_CTRL TMRB0_SCR TMRB0_CMPLD1 TMRB0_CMPLD2 TMRB0_COMSCR TMRB1_CMP1 TMRB1_CMP2 TMRB1_CAP TMRB1_LOAD TMRB1_HOLD TMRB1_CNTR TMRB1_CTRL TMRB1_SCR TMRB1_CMPLD1 ...
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Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8147 device Register Acronym TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR Table 4-13 Quad Timer ...
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Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR ...
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Table 4-14 Quad Timer D Registers Address Map Quad Timer D is NOT available in the 56F8147 device Register Acronym TMRD0_CMP1 TMRD0_CMP2 TMRD0_CAP TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR TMRD1_CMP1 TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8147 device Register Acronym TMRD2_CMPLD1 TMRD2_CMPLD2 TMRD2_COMSCR TMRD3_CMP1 TMRD3_CMP2 TMRD3_CAP TMRD3_LOAD TMRD3_HOLD TMRD3_CNTR TMRD3_CTRL TMRD3_SCR TMRD3_CMPLD1 TMRD3_CMPLD2 TMRD3_COMSCR Table 4-15 Pulse Width Modulator ...
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Table 4-15 Pulse Width Modulator A Registers Address Map (Continued) PWMA is NOT available in the 56F8147 device Register Acronym PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Table 4-16 Pulse Width Modulator B Registers Address Map Register Acronym PWMB_PMCTL PWMB_PMFCTL PWMB_PMFSA ...
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Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available in the ...
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Table 4-19 Interrupt Control Registers Address Map Register Acronym IPR 0 IPR 1 IPR 2 IPR 3 IPR 4 IPR 5 IPR 6 IPR 7 IPR 8 IPR 9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ADCA_LLMT 2 ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Table 4-21 Analog-to-Digital Converter Registers Address Map Register Acronym ADCB_CR 1 ADCB_CR 2 ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_HLMT 1 ADCB_HLMT 2 ADCB_HLMT 3 ADCB_HLMT 4 ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ADCB_OFS 0 ADCB_OFS 1 ADCB_OFS 2 ADCB_OFS 3 ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ...
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Table 4-24 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register ...
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Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB PLLSR SHUTDOWN OSCTL Table 4-29 GPIOA Registers Address Map Address Offset Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA 64 (CLKGEN_BASE = $00 ...
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Table 4-30 GPIOB Registers Address Map Register Acronym Address Offset GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Table 4-31 GPIOC Registers Address Map Register Acronym Address Offset GPIOC_PUR $0 GPIOC_DR $1 GPIOC_DDR $2 GPIOC_PER $3 GPIOC_IAR ...
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Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Table 4-33 GPIOE Registers Address Map Register Acronym Address Offset GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR ...
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Table 4-34 GPIOF Registers Address Map Register Acronym Address Offset GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR ...
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Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 68 (LVI_BASE = $00 F360) Address ...
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Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8147 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8147 device Register Acronym FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8147 device Register Acronym FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8147 device Register Acronym FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8147 device Register Acronym FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA 4.8 Factory Programmed Memory The ...
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Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump ...
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Table 5-2. Interrupt Priority Encoding IPIC_LEVEL[1: See IPIC field definition in 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A ...
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Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...
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Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL W R GPIOD $3 IPR3 IPL IPR4 SPI0_RCV ...
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Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0 IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the ...
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Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. ...
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Reserved—Bits 5–4 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.3.7 External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2 This field is used to set the interrupt ...
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GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
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FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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Interrupt Priority Register 5 (IPR5) Base + $ Read DEC1_XIRQ DEC1_HIRQ IPL Write RESET Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 ...
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SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Interrupt Priority Register 6 (IPR6) Base + $ Read TMRC0 IPL TMRD3 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—Bits 15–14 ...
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Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Fast Interrupt 0 Match Register (FIM0) Base + $ Read Write RESET Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not ...
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Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in ...
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Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address are ...
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IRQ Pending 2 Register (IRQP2) Base + $ Read Write RESET Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the ...
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IRQ Pending 5 Register (IRQP5) Base + $ Read Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The ...
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Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the ...
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IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes automatically level-sensitive. • IRQA interrupt is a low-level sensitive (default) • 1 ...
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Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system ...
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Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and ...
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Register Descriptions Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base + $6 SIM_MSH_ID Base + $7 SIM_LSH_ID Base ...
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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...
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EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result ...
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Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the ...
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Reserved—Bit 15 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.2 PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This bit ...
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CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are ...
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CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin. • 00000 = SYS_CLK (from OCCS - DEFAULT) • 00001 = Reserved for factory test—56800E clock • 00010 = Reserved for factory test—XRAM clock • ...
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Quad Timer Controlled SPI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Table 6-2 Control of Pads Using SIM_GPS Control Pin Function GPIO Input 0 GPIO Output 0 Quad Timer Input / 1 2 Quad Decoder Input Quad ...
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Base + $ Read Write RESET Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–4 This bit field is reserved or not implemented read as 0 and cannot ...
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External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.2 Analog-to-Digital Converter B ...
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Quad Timer B Enable (TMRB)—Bit 7 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 Quad Timer A ...
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I/O Short Address Location Register (SIM_ISALH and SIM_ISALL) The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower ...
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Base + $ Read Write RESET Figure 6-15 I/O Short Address Location Low Register (SIM_ISAL) 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” ...
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All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. 6.8 Stop and Wait Mode Disable Function ...
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After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of ...
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This security affords protection only to applications in which the device operates in internal Flash security mode. Therefore, the security feature cannot be used unless all executing code resides on-chip. When security is enabled, any attempt to override the default ...
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SYS_CLK 2 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the ...
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Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access ...
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Table 8-1 56F8347 GPIO Ports Configuration (Continued) Available GPIO Port Pins in Port Width 56F8347 6 pins - EMI CSn pins - SCI1 2 pins - EMI CSn 3 pins -PWMB current sense ...
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Table 8-3 GPIO External Signals Map Pins in italics are NOT available in the 56F8147 device GPIO Port GPIOA GPIOB 1 This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset. Freescale Semiconductor Preliminary Reset GPIO ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8147 device GPIO Port GPIOC GPIOD 126 Reset GPIO Bit Function 0 Peripheral PhaseA1 / TB0 / SCLK1 1 Peripheral PhaseB1 / TB1 / MOSI1 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8147 device GPIO Port GPIOE GPIOF 1. See Part 6.5.8 to determine how to select peripherals from this set Freescale Semiconductor Preliminary Reset GPIO Bit ...
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Part 9 Joint Test Action Group (JTAG) 9.1 JTAG Information Please contact your Freescale device/package-specific BSDL information. Part 10 Specifications 10.1 General Characteristics The 56F8347/56F8147 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to ...
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Note: The 56F8147 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8147 device. Table 10-1 Absolute Maximum Ratings Characteristic Supply Voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage ...
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Table 10-2 56F8347/56F8147 Electrostatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Four layer ...
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Note: The 56F8147 device is guaranteed to 40MHz and specified to meet Industrial requirements only. Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply ...
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DC Electrical Characteristics Note: The 56F8147 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8147 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output High Voltage V OH ...
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Table 10-6 Power-On Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below V ...
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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 800μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200 ...
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Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8147 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...
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AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...
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External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) 3 Clock Pulse Width 4 External clock input rise time 5 External clock input fall time 1. Parameters listed are guaranteed ...
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Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode ...
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DCAOE and DCAEO are calculated as follows: 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 DCAOE = = 0.0 all other cases MIN XTAL duty cycle - 0.5, if ...
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Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Valid Data Out Hold Time after WR Deasserted Valid Data Out Set-Up Time to WR Deasserted ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration RESET Deassertion to First External Address ...
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RESET t RAZ A0–A15, D0–D15 Figure 10-5 Asynchronous Reset Timing IRQA, IRQB Figure 10-6 External Interrupt Timing (Negative-Edge Sensitive) A0–A15, PS, DS, RD, WR, t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-7 ...
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IRQA, IRQB A0–A15, PS, DS, RD, WR, Figure 10-8 Interrupt from Wait State Timing t IW IRQA A0–A15, PS, DS, RD, WR, Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.10 Serial Peripheral Interface (SPI) Timing Characteristic Cycle ...
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Characteristic Clock (SCK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref) ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. ...
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Phase A (Input) Phase B (Input) Figure 10-15 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate 3 RXD RXD Pulse Width 4 TXD TXD Pulse Width 1. Parameters listed are guaranteed by design. 2. ...
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Controller Area Network (CAN) Timing Note: CAN is not available in the 56F8147 device. Characteristic Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) Figure 10-18 Bus Wake Up ...
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TCK (Input – Figure 10-19 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-20 Test Access Port Timing Diagram TRST ...
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Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , ...
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Table 10-24 ADC Parameters (Continued) Characteristic Total Harmonic Distortion Spurious Free Dynamic Range 8 Effective Number Of Bits 1. INL measured from V = .1V in REFH 10% to 90% Input Signal Range 2. LSB = Least Significant Bit 3. ...
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Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...
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Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & open, one ...
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C, the internal [dynamic component], is classic C*V 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly ...
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Part 11 Packaging Note: The 160 Map Ball Grid Array is not available in the 56F8147 device. 11.1 56F8347 Package and Pin-Out Information This section contains package and pin-out information for the 56F8347. This device comes in a 160-pin Low-profile ...
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Table 11-1 56F8347 160-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 43 4 TXD0 44 5 RXD0 45 6 PHASEA1 46 7 PHASEB1 47 ...
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Table 11-1 56F8347 160-Pin LQFP Package Identification by Pin Number (Continued) Signal Pin No. Pin No. Name 26 A15 DD_IO 32 D10 72 ...
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A INDEX0 D15 PHASEA0 B EMI_ HOME0 PHASEB0 TXD0 MODE PHASEA1 RXD0 PHASEB1 CLKO MISO0 E HOME1 INDEX1 ...
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Table 11-2 56F8347 -160 MAPBGA Package Identification by Pin Number Ball Ball Signal Name No. No K11 DD_IO CLKO N3 B1 TXD0 P2 D2 RXD0 M3 C1 PHASEA1 N4 D1 PHASEB1 P3 ...
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Table 11-2 56F8347 -160 MAPBGA Package Identification by Pin Number (Continued) Ball Ball Signal Name No. No. J3 A15 L10 K2 D9 P10 E5 V N10 DD_IO K4 D10 P11 ...
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X D LASER MARK FOR PIN 1 Y IDENTIFICATION IN THIS AREA E 0. 13X 3 b 160X 0. VIEW M-M 0.10 Z Figure 11-3 160 MAPBGA Mechanical Information ...
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Package and Pin-Out Information This section contains package and pin-out information for the 56F8147. This device comes in a 160-pin Low-profile Quad Flat Pack (LQFP). Figure 11-5 shows the mechanical parameters for this package, and 160-pin LQFP. Orientation ...
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Table 11-3 56F8147 160-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 43 4 TXD0 44 5 RXD0 45 6 SCLK1 46 7 MOSI1 47 ...
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Table 11-3 56F8147 160-Pin LQFP Package Identification by Pin Number (Continued) Signal Pin No. Pin No. Name 26 A15 DD_IO 32 D10 72 ...
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DETAIL F e 156X C e/2 4X SEATING PLANE θ2 θ3 S (L1) DETAIL F Figure 11-5 160-pin LQFP Mechanical Information Please see http://www.freescale.com for the most current mechanical drawing. 166 160X 0.20 C ...
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Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature θJΑ where Ambient temperature for the package ( ...
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small ...
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Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in ...
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... Technical Data, Rev.11 Ambient Temperature Order Number (MHz) Range 60 -40° 105°C MC56F8347VPY60 40 -40° 105°C MC56F8147VPY 60 -40° 105°C MC56F8347VPYE* 60 -40° 125°C MC56F8347MPYE* 40 -40° 105°C MC56F8147VPYE* 60 -40° 105°C MC56F8347VVF* Freescale Semiconductor Preliminary ...
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Freescale Semiconductor Preliminary 56F8347 Technical Data, Rev.11 Power Distribution and I/O Ring Implementation 171 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8347 Rev.11 01/2007 ...