STI7200 STMicroelectronics, STI7200 Datasheet - Page 2

• Manufacturer Part Number: STI7200
• Description: Triple Display, Hdtv Set-top Box, Dual Decoder For H.264 And Vc-1
• Manufacturer: STMicroelectronics

Description
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Description
The STi7200 is a new generation, high-definition set-top box/DVD decoder chip, and
provides very high performance for low-cost HD systems. With enhanced performance over
the STx7109, it includes both Windows Media Video 9 and H.264 video decoders for new,
low bitrate applications. The STi7200 is able to decode two HD programs.
Based on the STBus architecture, this system-on-chip is a full back-end processor for digital
terrestrial, satellite, cable and IP high-definition set-top boxes, compliant with ATSC, SMPTE
VC-1, DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications. The STi7200
includes all processing for DVD applications.
Applications
The STi7200 demultiplexes, decrypts and decodes HD or SD video streams with associated
multichannel audio. Video is output to three independently formatted displays:
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Connection to the main TV or display panel can be analog (RGB/YUV) through HD DACs, or
digital through a copy protected DVI/HDMI. Composite outputs are provided for connection
to local and remote TVs or VCR with Macrovision or Dwight Cavendish protection.
Audio is output with optional PCM mixing to an S/PDIF interface, dual PCM interface, or
through integrated dual stereo audio DACs.
Digitized analog programs can also be input to the STi7200 for reformatting and display.
The STi7200 includes a graphics rendering and display capability with a 2D graphics
accelerator. A triple display compositor mixes graphics and video with independent
composition for each of the TV and VCR or SDTV outputs. Picture In Picture (PIP) is
supported.
The STi7200 handles up to six external transport streams from different sources.
Four transport stream inputs, two transport stream input/outputs and two transport stream
outputs are supported. Applications include DVR time-shifted viewing of a terrestrial
program, while acquiring an EPG/data stream from a satellite or cable front end.
The transport architecure uncouples the transport packet processing from the transport
packet collection. The input transport streams are stored in SDRAM after PID filtering and
time stamp collection. DMAs fetch data from external memory and inject them to PTIs or
transport stream output ports.
The flexible descrambling engine is compatible with required standards including DVB, DES,
AES and Multi2.
The STi7200 has a 350 MHz ST40-210 CPU for applications and device control. A dual 32-
bit DDR2 SDRAM interface provides the required bandwidth for dual HD VC-1/H.264 video
decoding, and for the CPU and the rest of the system.
a full resolution display intended for a local HDTV monitor,
a downsampled display intended for a VCR or local SDTV,
an SD resolution display intended for a remote SDTV monitor.
CD00145658
STi7200