STI7100 STMicroelectronics, STI7100 Datasheet
STI7100
Available stocks
Related parts for STI7100
STI7100 Summary of contents
Page 1
... Low cost HDTV set-top box decoder for H.264/AVC and MPEG-2 Features ■ The STi7100 is a single-chip, high-definition STB decoder including: – ST40 CPU core, 266 MHz – dual ST231 CPU cores for audio and video decoding, both 400 MHz – transport filtering and descrambling – ...
Page 2
... The flexible descrambling engine is compatible with required standards including DVB, DES, AES and Multi2. The STi7100 embeds a 266 MHz ST40 CPU for applications and device control. A dual DDR1 SDRAM memory interface is used for higher performance, to allow the video decoder the required memory bandwidth for HD H.264 decoding and sufficient bandwidth for the CPU and the rest of the system ...
Page 3
... Mbit DDR1 DDR1 Transport stream in STi7100 Flash Smart cards ™ Flash interface 2 x 128 Mbit DDR1 EMI STV0498 Cable front end QAM/QPSK STi7100 transceiver IR Tx/Rx RS232 Smart cards Description RGB/YPbPr/ HDMI CVBS/YC VCR 2 x 128 Mbit DDR1 RGB/YPbPr/ HDMI CVBS/YC VCR 3/9 ...
Page 4
... PSTN MAFE I/F Figure 4. Low-cost HD IP-TV set-top box with HDD Flash Ethernet RJ45 4/9 2xDDR1 HDD EMI SATA STi7100 DVB-CI Smart cards 2xDDR1 HDD EMI SATA Ethernet STi7100 controller RS232 Smart cards IR Tx/Rx RGB/YPbPr/ HDMI RS232 USB 2.0 HDD (expansion) IR Tx/Rx RGB/YPbPr/ HDMI USB 2.0 HDD (expansion) STi7100 ...
Page 5
... STi7100 1.1 Detailed features list 1.1.1 Processor subsystem ● ST40 32-bit superscalar RISC CPU – 266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU – 5-stage pipeline, delayed branch support – floating point unit, matrix operation support – debug port, interrupt controller 1 ...
Page 6
... ROM, Flash, SFlash, SRAM, peripherals – access in 5 banks – master/slave support for interconnecting two STi7100 devices ● Dual local memory interface (LMI) – dual interface for 32-bit DDR1 200-MHz (DDR400) memories, supports 64, 128, 256 and 512 Mbit devices ● ...
Page 7
... STi7100 ● On-chip peripherals – 4 ASCs (UARTs) with Tx and Rx FIFOS, two of which can be used in smartcard interfaces – 2 smartcard interfaces and clock generators (improved to reduce external circuitry) – 3 SSCs for I²C/SPI master slaves interfaces – serial communications interface (SCIF) – 2 PWM outputs – ...
Page 8
... Revision history 2 Revision history Table 1. Document revision history Date 19-Dec-2006 10-Dec-2004 8/9 Revision 2 Rewritten to include latest information and corrected product code. 1 Initial release. STi7100 Changes ...
Page 9
... STi7100 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...