ST16C654D Exar Corporation, ST16C654D Datasheet - Page 12

• Manufacturer Part Number: ST16C654D
• Description: St16c654d -quad Uart With 64-byte Fifo And Infrared Irda Encoder/decoder
• Manufacturer: Exar Corporation

ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
The 654 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
2.8, Programmable Baud Rate Generator” on page 12
F
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in
generator for standard or custom rates. For further reading on oscillator circuit please see application note
DAN108 on EXAR’s web site.
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (2
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
2.7
2.8
IGURE
Figure
RXRDY#
TXRDY#
P
INS
5. T
Crystal Oscillator or External Clock Input
Programmable Baud Rate Generator
5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
T
YPICAL OSCILLATOR CONNECTIONS
ABLE
0 = 1 byte
1 = no data
0 = THR empty
1 = byte in THR
(FIFO D
5: TXRDY#
FCR
BIT
ISABLED
-0=0
AND
)
RXRDY# O
0 = at least 1 byte in FIFO
1 = FIFO empty
0 = FIFO empty
1 = at least 1 byte in FIFO
(DMA M
16
22-47pF
XTAL1
-1) to obtain a 16X sampling rate clock of the serial data rate. The
FCR B
C1
UTPUTS IN
ODE
R=300K to 400K
IT
D
-3 = 0
14.7456
ISABLED
MHz
12
FIFO
FCR B
)
22-47pF
XTAL2
C2
AND
IT
-0=1 (FIFO E
DMA M
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
ODE FOR
(DMA M
NABLED
FCR B
C
ODE
)
HANNELS
IT
-3 = 1
E
NABLED
xr
A-D
)
REV. 5.0.2
“Section