DS32C35 Maxim Integrated Products, Inc., DS32C35 Datasheet - Page 14

• Manufacturer Part Number: DS32C35
• Description: Accurate I2c Rtc With Integrated Tcxo/crystal/fram
• Manufacturer: Maxim Integrated Products, Inc.

Accurate I
TCXO/Crystal/FRAM
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the device switches to V
bit is clear (logic 0) when power is first applied. When
the device is powered by V
on regardless of the status of the EOSC bit.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1 and the device is being
powered by the V
wave or interrupt output when V
BBSQW is logic 0, the INT/SQW pin goes high imped-
ance when V
bit is disabled (logic 0) when power is first applied.
Bit 5: Convert Temperature (CONV). When the device
is in idle state, setting this bit to 1 forces the tempera-
ture sensor to convert the temperature into digital code
and execute the TCXO algorithm to update the capaci-
tance load for the oscillator. This can only happen
when a conversion is not already in progress. The user
should check the status bit BSY before forcing the con-
troller to start a new TCXO execution. A user-initiated
temperature conversion does not affect the internal 64-
second update cycle.
Table 5. Interrupt/Square-Wave Output
14
EOSC
BIT 7
INTCN
____________________________________________________________________
0
0
0
0
1
1
1
Special-Purpose Registers
CC
falls below the power-fail trip point. This
BBSQW
BAT
BIT 6
pin, this bit enables the square-
RS2
X
X
X
0
0
1
1
2
Control Register (0Eh)
C RTC with Integrated
CC
, the oscillator is always
CONV
BIT 5
CC
is absent. When
RS1
X
X
X
0
1
0
1
BAT
BIT 4
RS2
. This
A2F + A1F
1.024kHz
4.096kHz
8.192kHz
INT/SQW
OUTPUT
1Hz
A1F
A2F
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. Table 5 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set to logic 1 (8.192kHz)
when power is first applied.
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, then a match between the
timekeeping registers and either of the alarm registers
activates the INT/SQW output (if the alarm is also
enabled). The corresponding alarm flag is always set
regardless of the state of the INTCN bit. The INTCN bit
is set to logic 1 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
BIT 3
RS1
INTCN
0
0
0
0
1
1
1
INTCN
BIT 2
Control Register (0Eh)
A2IE
X
X
X
X
0
1
1
BIT 1
A2IE
A1IE
BIT 0
A1IE
X
X
X
X
1
0
1