S25FL128R Meet Spansion Inc., S25FL128R Datasheet - Page 26

• Manufacturer Part Number: S25FL128R
• Description: 128 Megabit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Bus
• Manufacturer: Meet Spansion Inc.

11.5
26
11.4.2
Write Enable (WREN: 06h)
Parallel Mode
The maximum clock frequency allowed on the SCK input pin in parallel mode is 10 MHz. The Parallel Mode
Entry command (55h) must be issued before writing the READ_ID command. Once in the parallel mode, the
flash memory will not exit parallel mode until a Parallel Mode Exit (45h) command is given to the flash device,
or upon power-down/power-up sequence.
The Write Enable (WREN) command (see
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
PO[7-0]
SCK
CS#
SI
Device Identification (Memory Capacity)
SO/PO[7-0]
Manufacturer Identification
0
D a t a
CS#
SCK
1
Description
SI
Figure 11.8 Write Enable (WREN) Command Sequence
2
High Impedance
Figure 11.7 Parallel Read_ID Instruction Sequence
Instruction
Mode 3
Mode 0
Hi-Z
90h
3
Table 11.2 READ_ID Command and Data
S h e e t
4
5
0 1 2 3 4 5 6 7
S25FL128R
6
Figure
7
MSB
( A d v a n c e
15
8
Command
14
11.8) sets the Write Enable Latch (WEL) bit to a 1, which
9
13
1
2 Dummy
0
Bytes
2
3
0
2
2
1
I n f o r m a t i o n )
22
1
Address
00000h
00001h
2
0
3
7
2
S25FL128R_00_02 December 1, 2009
4
6
2
5
5
2
6
ADD (1)
Manufacture ID
4
2
7
3
2
8
Device ID
2
2
9
1
3
0
Data
01h
17h
0
3
1
Byte
1
3
2
Byte
2
3
3
3
4