XC3S1000L Xilinx Corp., XC3S1000L Datasheet - Page 6

• Manufacturer Part Number: XC3S1000L
• Description: Spartan-3l Low Power Fpga Family
• Manufacturer: Xilinx Corp.

Spartan-3L Low Power FPGA Family
Functional Description
The Spartan-3L FPGA family is identical to the Spartan-3
FPGA family with respect to device function. See the func-
tional description in Module 2 of the Spartan-3 data sheet
(
Achieving Low Quiescent Current Levels
Because of their lower quiescent current specifications,
Spartan-3L devices always consume less power than
Spartan-3 devices.
For power-sensitive applications that must manage con-
sumption over long periods with no FPGA activity, it is pos-
sible to achieve the quiescent current levels specified in
Table 4
on
the table. The easiest way to realize these conditions is by
pulling PROG_B Low. This action puts all I/Os into a
high-impedance state, ceases all internal switching, and
converts the bitmap held in internal memory to all zeros.
During and after the Low pulse on PROG_B, disable the
internal pull-up resistors on all I/Os by keeping HSWAP_EN
High. Reconfiguration is necessary before the FPGA can
resume operation in the User mode.
As an alternate approach, when it is desirable to retain the
programmed bitmap, do not assert PROG_B. If all other test
conditions are met (e.g., no internal switching, I/Os are off),
quiescent current levels will be very close to or slightly
above what is specified in
make sure internal pull-up and pull-down resistors on all
I/Os are disabled.
Hibernate Mode
Hibernate mode starts with the approach described above.
This takes power savings one step further by switching off
power rails. This mode reduces quiescent power consump-
6
DS099
page 9
) for more information.
of the
by meeting the test conditions described below
DC and Switching Characteristics
Table 4, page
9. In this case,
section
www.xilinx.com
tion to the lowest possible level. The FPGA is put into the
Hibernate mode by switching off the V
V
V
page 7
FPGAs into the Hibernate mode.
During the Hibernation period, the V
are turned off. It is recommended that power FETs with low
on resistance be used to perform the switching action. Con-
figuration data is lost upon entering the Hibernate mode;
therefore, reconfiguration is necessary after exiting the
mode.
In general, it is safest to maintain V
throughout the Hibernation period. This keeps the power
diodes inside the IOBs off when signals are applied to the
pins. For each I/O, a power diode extends from the pin (the
anode side) to the associated V
Power diodes are present on all signal-carrying pins all of
the time. In Hibernate mode, the powered V
account for little current, because the I/Os are in a
high-impedance state.
It is also possible to switch off the V
bank. This action eliminates the V
banks—current on the order of a few milliamperes. There
are two ways to achieve this. One way is to keep the voltage
of all I/Os belonging to that bank under 0.5V. Another way is
to disable signals coming from external devices (such as
Device 1 in
Holding the PROG_B input Low during the transition into
Hibernation period keeps all output drivers in a high-imped-
ance state. Release PROG_B after re-applying power to the
V
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Dual-Purpose pins.
CCAUX
CCO
CCINT
lines throughout the hibernation period.
is a block diagram that shows how to put Spartan-3L
and V
(auxiliary) power supplies. Power is supplied to
for recommended levels on Dedicated and
Figure
CCAUX
3).
rails. See
CCO
Special Considerations,
DS313 (v1.2) April 18, 2008
CCO
CCINT
CCO
CCO
rail (the cathode side).
Product Specification
power for all banks
rail for a particular
CCINT
current for those
and V
CCAUX
(core) and
CCO
Figure 3,
rails
rails
R