XC3S50A Xilinx Corp., XC3S50A Datasheet - Page 5

• Manufacturer Part Number: XC3S50A
• Description: Spartan-3a Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Configuration
Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
•
•
•
•
•
•
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
DS529-1 (v1.4.1) July 10, 2007
Product Specification
Notes:
1.
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Master Serial from a
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
Device
R
User
108
(7)
-
-
-
-
TQG144
TQ144
Xilinx Platform Flash PROM
(24)
Diff
50
-
-
-
-
User
144
195
(35)
195
(35)
(32)
-
-
FTG256
FT256
Diff
(32)
(50)
(50)
64
90
90
-
-
www.xilinx.com
User
(56)
(59)
248
251
-
-
-
FGG320
FG320
I/O Capabilities
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards.
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in
Spartan-3A FPGAs support the following single-ended
standards:
•
•
•
•
•
Spartan-3A FPGAs support the following differential
standards:
•
•
•
•
•
(64)
(64)
Diff
112
112
-
-
-
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
User
(63)
(63)
311
311
-
-
-
FGG400
FG400
Introduction and Ordering Information
Diff
142
(78)
142
(78)
-
-
-
User
372
(84)
375
(87)
-
-
-
FGG484
Table
FG484
(93)
(93)
2.
Diff
165
165
-
-
-
User
(94)
502
FGG676
-
-
-
-
FG676
Table 2
(131)
Diff
227
-
-
-
-
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