PIC16HV785 Microchip Technology Inc., PIC16HV785 Datasheet
PIC16HV785
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PIC16HV785 Summary of contents
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... Two-Phase Asynchronous Feedback PWM Dual High-Speed Comparators and © 2006 Microchip Technology Inc. PIC16F785/HV785 Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontroller with Dual Operational Amplifiers Preliminary DS41249D ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ © 2006 Microchip Technology Inc. ...
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... Capture, Compare, PWM module: - 16-bit Capture, max resolution 12 Compare, max resolution 200 ns - 10-bit PWM with 1 output channel, max frequency 20 kHz • In-Circuit Serial Programming pins • Shunt Voltage Regulator (PIC16HV785 only volt regulation - shunt range Preliminary ) DD TM (ICSP ...
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... PIC16F785/HV785 Program Data Memory Memory Device Flash SRAM EEPROM (words) (bytes) (bytes) PIC16F785 2048 128 256 PIC16HV785 2048 128 256 Dual in Line Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1 RC4/C2OUT/PH2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- RC7/AN9/OP1+ RB7/SYNC TABLE 1: DUAL IN LINE PIN SUMMARY ...
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... RC6 5 AN8 — RC7 6 AN9 — — 18 — — — 17 — — Note 1: Input only. 2: Open drain. © 2006 Microchip Technology Inc. PIC16F785/HV785 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT 14 RC0/AN4/C2IN RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 PIC16F785/HV785 Op PWM Timers CCP Amps — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41249D-page 4 ® Devices....................................................................................................................... 171 Preliminary © 2006 Microchip Technology Inc. ...
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... T1G T1CKI Timer0 Timer1 T0CKI Analog-to-Digital Converter © 2006 Microchip Technology Inc. PIC16F785/HV785 The PIC16F785/HV785 is covered by this Data Sheet available in 20-pin PDIP, SOIC, SSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F785/HV785 device. Table 1-1 shows the pinout description. ...
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... A/D Channel 11 input — Amp 2 non-inverting input TTL OD PORTB I/O. Open drain output TTL CMOS PORTB I/O ST CMOS Master PWM Sync output or slave PWM Sync input TTL CMOS PORTC I/O AN — A/D Channel 4 input AN — Comparator 2 non-inverting input Preliminary Description © 2006 Microchip Technology Inc. ...
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... RC7 AN9 OP1 Legend: TTL = TTL input buffer Schmitt Trigger input buffer Analog Open Drain output High Voltage © 2006 Microchip Technology Inc. PIC16F785/HV785 Input Output Type Type TTL CMOS PORTC I/O AN — A/D Channel 5 input AN — Comparator 1 and 2 inverting input — ...
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... PIC16F785/HV785 NOTES: DS41249D-page 8 Preliminary © 2006 Microchip Technology Inc. ...
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... Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory © 2006 Microchip Technology Inc. PIC16F785/HV785 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into four banks, which contain the General Purpose Regis- ters (GPR) and the Special Function Registers (SFR). ...
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... TRISC 187h 188h 189h PCLATH 18Ah INTCON 18Bh PIE1 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1EFh accesses 1F0h Bank 0 1FFh Bank 3 © 2006 Microchip Technology Inc. ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). © 2006 Microchip Technology Inc. PIC16F785/HV785 Bit 5 Bit 4 Bit 3 ...
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... IOCA1 IOCA0 37,114 --00 0000 — — CVROE — 72,114 --00 000- VR1 VR0 71,114 000- 0000 EEDAT1 EEDAT0 0000 0000 103,114 EEADR1 EEADR0 0000 0000 103,114 WR RD ---- x000 104,114 ---- ---- 104,114 81,114 xxxx xxxx — — 84,114 -000 ---- © 2006 Microchip Technology Inc. ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). © 2006 Microchip Technology Inc. PIC16F785/HV785 Bit 5 Bit 4 Bit 3 ...
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... Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). ...
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... W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 CCP1IE C2IE C1IE OSFIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Note 1: BOREN<1:0> Configuration Word for this bit to control the BOR. Legend Readable bit -n = Value at POR DS41249D-page 20 U-0 U-0 R/W-1 U-0 (1) — — SBOREN — ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-x — POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... CALL instruction (or interrupt) is executed, the entire 13-bit PC return address is PUSHed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the RETURN or RETFIE instructions (which POPs the address from the stack). © 2006 Microchip Technology Inc. PIC16F785/HV785 FIGURE 2-3: PCH 12 PC ...
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... Bank Select 180h Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR ;increment pointer ;all done? NEXT ;no clear next ;yes continue Indirect Addressing File Select Register 0 7 Location Select 1FFh © 2006 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2006 Microchip Technology Inc. PIC16F785/HV785 The PIC16F785/HV785 can be configured in one of eight clock modes – External clock with I/O on RA4 – 32.768 kHz Watch Crystal or Ceramic Resonator Oscillator mode. ...
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... Following a wake-up from Sleep mode or (1) CPU Start-up POR, CPU start-up is invoked to allow the CPU to become ready for code execution. 1024 Clock Cycles (OST (approx.) FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION Clock from Ext. System RA4 Preliminary © 2006 Microchip Technology Inc. Comments OSC1/CLKIN PIC16F785/HV785 I/O (OSC2) ...
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... Always verify oscillator performance over the V and temperature range that is DD expected for the application. © 2006 Microchip Technology Inc. PIC16F785/HV785 FIGURE 3- Ceramic Resonator Note 1: A series resistor (R ceramic resonators with low drive level. ...
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... The user also needs to take into account EXT variation due to tolerance of external RC components used. Internal Clock 3.0V) DD 3.0V) DD Preliminary RCIO MODE Internal OSC1 Clock PIC16F785/HV785 I/O (OSC2) R 100 k (V 3.0V) EXT 100 k (V 3.0V) EXT DD C > EXT ) and capacitor (C ) EXT EXT © 2006 Microchip Technology Inc. ...
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... Two-Speed Start enabled (IESO = 1 and IRCF 000). The HF Internal Oscillator (HTS) bit, (OSCCON<2>), indicates whether the HFINTOSC is stable or not. © 2006 Microchip Technology Inc. PIC16F785/HV785 3.4.2.1 The 8 MHz High-frequency Internal Oscillator (HFIN- TOSC) is factory calibrated. The HFINTOSC calibra- tion bits are stored in the Calibration Word (CALIB) located in program memory location 2008h ...
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... Monitor (FSCM) and peripherals, are not affected by the change in frequency. U-0 U-0 R/W-0 R/W-0 — — TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Note: Following any Reset, the IRCF bits are set to ‘110’ and the frequency selection is forced to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2006 Microchip Technology Inc. PIC16F785/HV785 3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFIN- TOSC, the new oscillator may already be shut down to save power ...
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... System clock is switched to external clock source. 3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC16F785/HV785 is running from the external clock source as defined by the F Configuration Word (CONFIG) or the internal oscillator. Preliminary bits in the OSC © 2006 Microchip Technology Inc. ...
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... OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. © 2006 Microchip Technology Inc. PIC16F785/HV785 ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed. DS41249D-page 32 Oscillator Failure CM Test Preliminary © 2006 Microchip Technology Inc. Failure Detected CM Test ...
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... CONFIG CPD CP Legend unknown unchanged, – = unimplemented locations read as ‘0’ value depends on condition. Shaded cells are not used by oscillators. Note 1: See Register 15-1 for operation of all Configuration Word bits. © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-1 R/W-0 R-q (1) IRCF1 IRCF0 OSTS ( value depends on condition W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC16F785/HV785 NOTES: DS41249D-page 34 Preliminary © 2006 Microchip Technology Inc. ...
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... Register 12-1). Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs ...
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... WPUA5 WPUA4 WPUA3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 (1) TRISA2 TRISA1 TRISA0 bit Bit is unknown (1), (2) R/W-1 R/W-1 R/W-1 (3) WPUA2 WPUA1 WPUA0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the inter- rupt by: a) Any read or write of PORTA ...
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... TRISA I/O pin RD TRISA PORTA IOCA RD IOCA Q1 Interrupt-on- change Q3 To Comparators To A/D Converter Preliminary /ICSPCLK REF BLOCK DIAGRAM OF RA1 V DD Weak Q Q RAPU I/O pin PORTA © 2006 Microchip Technology Inc. ...
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... D Interrupt-on- EN Change RD PORTA To TMR0 To INT To A/D Converter © 2006 Microchip Technology Inc. PIC16F785/HV785 4.2.3.4 Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • General purpose input • Master Clear Reset with weak pull-up FIGURE 4-4: Data Bus ...
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... When using Timer1 with LP oscillator, the Preliminary RA5/T1CKI/OSC1/CLKIN BLOCK DIAGRAM OF RA5 INTOSC Mode (1) CLK modes Weak Q RAPU V Oscillator DD Circuit OSC2 Q I/O pin INTOSC Mode ( PORTA Schmitt Trigger is bypassed. © 2006 Microchip Technology Inc. ...
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... CM1CON0 C1ON C1OUT 11Bh CM2CON1 MC1OUT MC2OUT Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2006 Microchip Technology Inc. PIC16F785/HV785 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 ...
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... Bit is set ‘0’ = Bit is cleared Preliminary INITIALIZING PORTB ;Bank 0 ; ;Init PORTB ;Bank 1 ;digital I/O - RB4 ;digital I/O - RB5 ;Set RB<5:4> as inputs ;and set RB<7:6> ;as outputs ;Bank 0 U-0 U-0 U-0 — — — bit Bit is unknown U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... TRISB ANS10 (RB4) ANS11 (RB5) RD TRISB PORTB To A/D Converter To Op Amp 2 © 2006 Microchip Technology Inc. PIC16F785/HV785 4.3.1.3 RB6 The RB6 pin is configurable to function as the following: • Open drain general purpose I/O FIGURE 4-8: Data Bus PORTB ...
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... ANS9 BLANK2 BLANK1 SYNC1 SYNC0 PH2EN — — — — — Preliminary Value on: Value on all Bit 0 POR, BOR other Resets — xxxx ---- uuuu ---- — 1111 ---- 1111 ---- ANS8 ---- 1111 ---- 1111 PH1EN 0000 0000 0000 0000 — 0--- ---- 0--- ---- © 2006 Microchip Technology Inc. ...
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... PORTC pin configured as an input (tri-stated PORTC pin configured as an output Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 When RC4 or RC5 is configured amp output, the corresponding RC4 or RC5 digital output driver will automatically be disabled regardless of the TRISC<4> ...
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... Analog input to Comparators 1 and 2 • Digital output from the Two-Phase PWM FIGURE 4-11: PH1EN PH1 Data Bus PORTC TRISC RD TRISC RD PORTC To Comparators To A/D Converter V DD I/O Pin V SS Preliminary BLOCK DIAGRAM OF RC1 I/O Pin V SS ANS5 © 2006 Microchip Technology Inc. ...
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... ANS6 (RC2) ANS7 (RC3) RD TRISC PORTC To Comparators To A/D Converter © 2006 Microchip Technology Inc. PIC16F785/HV785 4.4.1.7 RC4/C2OUT/PH2 The RC4 is configurable to function as one of the following: • General purpose I/O • Digital output from Comparator 2 • Digital output from the Two-Phase PWM FIGURE 4-13: C2OE ...
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... Bit 0 POR, BOR other Resets RC0 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 ANS0 1111 1111 1111 1111 ANS8 ---- 1111 ---- 1111 PH1EN 0000 0000 0000 0000 — 0--- ---- 0--- ---- — 0--- ---- 0--- ---- © 2006 Microchip Technology Inc. ...
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... INTRC Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2-2). 2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2). © 2006 Microchip Technology Inc. PIC16F785/HV785 Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/AN2/T0CKI/INT/C1OUT ...
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... TMR0, ; prescale, and ; clock source ; ;Bank 0 Value on Value on: Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu RAIF 0000 0000 0000 0000 PS0 1111 1111 1111 1111 ANS0 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...
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... ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI. Note 1: Timer1 increments on the rising edge. 2: SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9-2 on 66). © 2006 Microchip Technology Inc. PIC16F785/HV785 The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module ...
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... Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit (T1CON<7>), whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active high or active low time between events. Preliminary © 2006 Microchip Technology Inc. ...
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... Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit (CM2CON1<1>), as a Timer1 gate source. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 (2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC ...
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... TMR2IF TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1CS TMR1ON 0000 0000 uuuu uuuu T1GSS C2SYNC 00-- --10 00-- --10 TMR2IE TMR1IE 0000 0000 0000 0000 ANS1 ANS0 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...
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... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 7.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset ...
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... Bit 0 all other POR, BOR Resets INTF RAIF 0000 0000 0000 0000 TMR2IF TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 -000 0000 -000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...
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... Compare mode, trigger special event (CCP1IF bit is set; TMR1 is reset, and A/D conversion is started if the A/D module is enabled. CCP1 pin is unaffected.) 110x = PWM mode: CCP1 output is high true. 111x = PWM mode: CCP1 output is low true. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 TABLE 8-1: CCP Mode Capture Compare PWM ...
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... CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value COMPARE MODE OPERATION BLOCK DIAGRAM Mode Select Set Flag bit CCP1IF (PIR1<5>) 4 CCPR1H CCPR1L S Output Comparator Logic Match R TMR1H TMR1L © 2006 Microchip Technology Inc. ...
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... ADIE CCP1IE Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare or Timer1 module. © 2006 Microchip Technology Inc. PIC16F785/HV785 8.2.4 SPECIAL EVENT TRIGGER In this mode (CCP1M<3:0> = 1011), an internal hardware trigger is generated, which may be used to initiate an action ...
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... Operation”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. RC5/CCP1 TRISC<5> Preliminary PWM PERIOD = PR2 + OSC (TMR2 prescale value) © 2006 Microchip Technology Inc. ...
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... Maximum Resolution (bits) 10 Note 1: Changing duty cycle will cause a glitch. © 2006 Microchip Technology Inc. PIC16F785/HV785 CCPR1L and DC1B<1:0> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs DC1B< ...
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... CCP1M0 0000 0000 0000 0000 TRISC1 TRISC0 --11 1111 --11 1111 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 © 2006 Microchip Technology Inc. ...
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... AN<7:5,1>. Note: To use AN<7:5,1> as analog inputs the appropriate bits must be programmed to ‘1’ in the ANSEL0 register. © 2006 Microchip Technology Inc. PIC16F785/HV785 Setting C1R (CM1CON0<2>) selects the C1V put of the comparator voltage reference module as the reference voltage for the comparator. Clearing C1R selects the C1IN+ input on the RA0/AN0/C1IN+/ ICSPDAT pin ...
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... Output shown for reference only. For more detail, see Figure 4-3. DS41249D-page MUX 2 Q3*RD_CM1CON0 3 (1) C1ON C1SP C1VN 0 C1 C1VP MUX 1 C1POL Preliminary C1POL Data Bus EN RD_CM1CON0 Set C1IF PWM Logic CL NRESET C1OE C1OUT (2) RA2/AN2/T0CKI/INT/C1OUT © 2006 Microchip Technology Inc. ...
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... C1VN of C1 connects to RA1/AN1/C12IN0-/ C1VN of C1 connects to RC1/AN5/C12IN1-/PH1 10 = C1VN of C1 connects to RC2/AN6/C12IN2-/OP2 11 = C1VN of C1 connects to RC3/AN7/C12IN3-/OP1 Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if: (C1OE = 1) and (C1ON = 1) and (TRISA<2> = 0). Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 R-0 R/W-0 R/W-0 R/W-0 C1OE C1POL C1SP ...
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... From TMR1 MUX Clock 1 Preliminary C2 OUTPUT STATE VERSUS INPUT CONDITIONS C2POL C2OUT (TRISA<4> = 0). C2POL Data Bus EN RD_CM2CON0 Set C2IF NRESET To PWM Logic C2OUT C2SYNC C20E 0 MUX RC4/C2OUT/PH2 (2) SYNCC2OUT © 2006 Microchip Technology Inc. (3) ...
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... C2VN of C2 connects to RA1/AN1/C12IN0-/ C2VN of C2 connects to RC1/AN5/C12IN1-/PH1 10 = C2VN of C2 connects to RC2/AN6/C12IN2-/OP2 11 = C2VN of C2 connects to RC3/AN7/C12IN3-/OP1 Note 1: C2OUT will only drive RC4/C2OUT/PH2 if: (C2OE = 1) and (C2ON = 1) and (TRISC<4> = 0). Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 R/W-0 C2OE C2POL C2SP ...
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... C2 output is synchronous to falling edge of TMR1 clock output is asynchronous Legend Readable bit -n = Value at POR DS41249D-page 68 U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-0 T1GSS C2SYNC bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment. © 2006 Microchip Technology Inc. PIC16F785/HV785 9.3 Comparator Interrupts The comparator interrupt flags are set whenever there is a change in the output value of its respective compar- ator ...
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... Table 19-8. Preliminary CV OUTPUT VOLTAGE REF = VR<3:0> / /4) + (VR<3:0> /32 cannot be realized due from approaching V or REF SS when VR<3:0> SS module current. REF derived and therefore, the DD . The DD © 2006 Microchip Technology Inc. ...
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... When VRR = 0 and CVREN = 1: CV When CxVREN = 0 and VREN = 1: CxV Note 1: When C1VREN, C2VREN and CVROE (Register 10-2) are all low, the CV is powered down and does not contribute to I Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 16 Stages MUX 15 · ...
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... CVROE: Comparator Voltage Reference Output Enable bit (see Figure 10- output on RA1/AN1/C12IN0-/V REF output on RA1/AN1/C12IN0-/V REF bit 0 Unimplemented: Read as ‘0’ Note 1: Buffer amplifier common mode limitations require V output. 2: VREN is fixed high for PIC16HV785 device. Legend Readable bit -n = Value at POR DS41249D-page 72 REF U-0 R-0 R/W-0 R/W-0 — ...
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... FIGURE 10-2: VR REFERENCE BLOCK DIAGRAM VREN CV CVROE REF EN Voltage Reference RDY Note 1: Buffered output requires VR 2: VREN is fixed high for PIC16HV785 device. TABLE 10-1: REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Address Name Bit 7 Bit 6 119h CM1CON0 C1ON C1OUT 11Ah CM2CON0 ...
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... PIC16F785/HV785 NOTES: DS41249D-page 74 Preliminary © 2006 Microchip Technology Inc. ...
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... OPA MODULE BLOCK DIAGRAM RC7/AN9/OP1+ RC6/AN8/OP1- RC3/AN7/C12IN3-/OP1 RB5/AN11/OP2+ RB4/AN10/OP2- RC2/AN6/C12IN2-/OP2 © 2006 Microchip Technology Inc. PIC16F785/HV785 11.2 OPAxCON Register The OPA module is enabled by setting the OPAON bit (OPAxCON<7>). When enabled, OPAON forces the output driver of RC3/AN7/C12IN3-/OP1 for OPA1, and ...
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... Bit is cleared U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit Bit is unknown U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for the OPA module. © 2006 Microchip Technology Inc. PIC16F785/HV785 Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To mini- ...
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... PIC16F785/HV785 NOTES: DS41249D-page 78 Preliminary © 2006 Microchip Technology Inc. ...
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... RA2/AN2/T0CKI/INT/C1OUT RA4/AN3/T1G/OSC2/CLKOUT RC0/AN4/C2IN+ RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- RC7/AN9/OP1+ RB4/AN10/OP2- RB5/AN11/OP2+ CV REF VR CHS<3:0> Note 1: When ADON = 0 all input channels are disconnected from ADC (no loading). © 2006 Microchip Technology Inc. PIC16F785/HV785 V DD VCFG = 0 V VCFG = 1 REF 0 A/D GO/DONE ADFM (1) ADON V SS ...
Page 82
... DD is used. The VCFG bit (ADCON0<6>) pin is the reference; REF is the reference. . The source calculations for AD 4 MHz 1.25 MHz (2) 500 ns 1.6 s (2) 1.0 s 3.2 s 2.0 s 6.4 s (3) 4.0 s 12.8 s (3) (3) 8.0 s 25.6 s (3) (3) 16.0 s 51.2 s (1), (4) (1), (4) 2-6 s 2-6 s © 2006 Microchip Technology Inc. ...
Page 83
... ADRESH (ADDRESS:1Eh) (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC16F785/HV785 If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion ADRESH:ADRESL registers will retain the value of the previous conversion ...
Page 84
... AN7 AN6 AN5 AN4 RC6 RC3 RC2 RC1 RC0 Preliminary R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown R/W-1 R/W-1 R/W-1 ANS10 ANS9 ANS8 bit Bit is unknown ANS3 ANS2 ANS1 ANS0 AN3 AN2 AN1 AN0 RA4 RA2 RA1 RA0 © 2006 Microchip Technology Inc. ...
Page 85
... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Enable bit 1 = A/D converter module is enabled 0 = A/D converter is shut-off and consumes no operating current Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 R/W-0 CHS3 CHS2 CHS1 CHS0 W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 86
... Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR DS41249D-page 84 R/W-0 R/W-0 U-0 ADCS1 ADCS0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 87
... For next conversion step 1 or step 2 as required. The A/D conversion time per bit is defined minimum wait required before the next acquisition starts. © 2006 Microchip Technology Inc. PIC16F785/HV785 EXAMPLE 12-1: ;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and RA0 input. ...
Page 88
... HOLD Preliminary the minimum acquisition time, , see ACQ ® Mid-Range MCU Family Reference 5. Temperature Coefficient © 2006 Microchip Technology Inc. ...
Page 89
... Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD © 2006 Microchip Technology Inc. PIC16F785/HV785 V DD Sampling Switch LEAKAGE V = 0.6V T ± 500 nA ...
Page 90
... When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted and the A/D module is turned off. The RC ADON bit remains set. Full-Scale Range 1 LSb ideal Full-Scale Transition Analog Input Voltage 1 LSb ideal V Zero-Scale REF Transition Preliminary © 2006 Microchip Technology Inc. ...
Page 91
... ADCS2 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module. © 2006 Microchip Technology Inc. PIC16F785/HV785 The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion) ...
Page 92
... PIC16F785/HV785 NOTES: DS41249D-page 90 Preliminary © 2006 Microchip Technology Inc. ...
Page 93
... The phase output remains true until terminated by a feedback signal from either of the comparators or the auto-shutdown activates. Phase granularity is a function of the period count value. For example, if PER<4:0> each output can be shifted in 90 steps (see Equation 13-2) © 2006 Microchip Technology Inc. PIC16F785/HV785 EQUATION 13-2: Phase 13.3 PWM Duty Cycle ...
Page 94
... RA2/AN2/T0CKI/INT/C1OUT pin). IH PH1EN PH2EN PWMASE SHUTDOWN PASEN pwm_clk Phase Res Counter 5 PER<4:0> pwm_count 5 PWMPH1<4:0> SHUTDOWN PH1EN 5 PWMPH2<4:0> SHUTDOWN PH2EN Preliminary MASTER RB7/SYNC 5 PWMPH1<POL> S pha1 Q (1) R RC1/AN5/C12IN1-/PH1 PWMPH2<POL> S pha2 Q (1) R RC4/C2OUT/PH2 © 2006 Microchip Technology Inc. ...
Page 95
... The PH1 pin is driven by the PWM signal 0 = The PH1 pin is not used for PWM functions Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0> bits in the PWMCON1 register (Register 13-5) for more information. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 R/W-0 BLANK2 ...
Page 96
... Legend Readable bit -n = Value at POR DS41249D-page 94 R/W-0 R/W-0 R/W-0 PWMP0 PER4 PER3 1 OSC 2 OSC 4 OSC 8 OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 PER2 PER1 PER0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 97
... Complementary drive start is delayed by 1 pwm_clk pulse ••••• = • • • 11111 = Complementary drive start is delayed by 31 pwm_clk pulses Note 1: See PWMCON1 register (Register 13-5). Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 R/W-0 C1EN ...
Page 98
... All other PH2 delays are expressed relative to this time. ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 PH2 PH1 PH0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 99
... Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2 FIGURE 13-3: TWO-PHASE PWM START-UP TIMING F OSC PWMP<1:0> 01, PER<4:0> pwm_clk pwm_count SYNC PHnEN pwm_clk pwm_count PHnEN © 2006 Microchip Technology Inc. PIC16F785/HV785 Preliminary ...
Page 100
... PWM drive pulses into Q1. If the output voltage is too high, then the voltage to the non-inverting input of Comparator 1 will fall, resulting in shorter PWM drive pulses into Q1. PIC16F785 F OSC FET Driver PH1 T -Phase WO PWM Preliminary © 2006 Microchip Technology Inc. V UNREG ...
Page 101
... MOVWF VRCON ;see data sheet page 71 ;Everything is setup at this point so now it is time to enable PH1 BANKSEL PWMCON0 BSF PWMCON0,PH1EN ;enable PH1 ;Module is running autonomously at this point © 2006 Microchip Technology Inc. PIC16F785/HV785 on, low range REN REF DD Preliminary , -:AN6 REF ...
Page 102
... During shutdown the PH1 and PH2 complementary outputs are forced to their inactive states (see Figure 13-5). When shutdown ceases the PWM out- puts revert to their start-up states for the first cycle which is PH1 inactive (output undriven) and PH2 active (output driven). values of Preliminary © 2006 Microchip Technology Inc. ...
Page 103
... OSC Prescale 5 PWMPH1<4:0> 5 PWMPH2<4:0> PWMPH1<C1EN> C1OUT PWMPH1<C2EN> C2OUT COMOD<1:0> Note 1: Reset dominant. © 2006 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 COMOD0 CMDLY4 CMDLY3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PH1EN pwm_reset ...
Page 104
... C2CH0 0000 0000 0000 0000 CMDLY0 -000 0000 -000 0000 PH1EN 0000 0000 0000 0000 PER1 PER0 0000 0000 0000 0000 PH1 PH0 0000 0000 0000 0000 PH1 PH0 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...
Page 105
... EEADR: Specifies one of 256 locations for EEPROM Read/Write Operation bits Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC16F785/HV785 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
Page 106
... EEPROM write (WR bit = 1). U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘S’ = Bit can only be set ‘0’ = Bit is cleared Preliminary R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 107
... WREN bit clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. © 2006 Microchip Technology Inc. PIC16F785/HV785 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...
Page 108
... WREN Preliminary Value on all Value on: Bit 0 other POR, BOR Resets RAIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ---- © 2006 Microchip Technology Inc. ...
Page 109
... The INTOSC option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 15-1). © 2006 Microchip Technology Inc. PIC16F785/HV785 15.1 Configuration Bits The configuration bits can be programmed (read as ‘ ...
Page 110
... Value at POR DS41249D-page 108 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 (5) (1) (2), (3) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary bit 0 (5) ( Bit is unknown © 2006 Microchip Technology Inc. ...
Page 111
... Ripple Counter LFINTOSC Note 1: Refer to the Configuration Word register (Register 15-1). © 2006 Microchip Technology Inc. PIC16F785/HV785 They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 15-2. These bits are used in software to determine the nature of the Reset ...
Page 112
... PP to rise to an acceptable level. A config- for details (Section 19.0 for greater than parameter BOR slew rate. A Reset DD falls below V for less than DD BOR ). rises above DD while the Power-up Timer is BOR DD , the Power-up Timer will execute a BOR © 2006 Microchip Technology Inc. ...
Page 113
... FIGURE 15-3: BROWN-OUT SITUATIONS V DD Internal Reset V DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2006 Microchip Technology Inc. PIC16F785/HV785 Specification” (2000h- Specification” ( < Preliminary V BOR V BOR ...
Page 114
... Z DC — SBOREN — — POR Preliminary may have DD Wake-up from Sleep PWRTE = 1 + 1024•T 1024•T OSC OSC — — Value on all Value on: Bit 0 other POR, BOR (1) Resets C 0001 1xxx 000q quuu BOR ---1 --qq ---u --uu © 2006 Microchip Technology Inc. ...
Page 115
... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 15-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2006 Microchip Technology Inc. PIC16F785/HV785 T PWRT T OST T PWRT T OST DD T PWRT T OST Preliminary ) ...
Page 116
... Microchip Technology Inc. ...
Page 117
... If Reset was due to brown-out, then bit All other Resets will cause bit Analog channels read 0 but data latches are unknown. 7: Analog channels read 0 but data latches are unchanged. © 2006 Microchip Technology Inc. PIC16F785/HV785 Wake-up from Sleep through interrupt MCLR Reset Wake-up from Sleep through WDT Time-out ...
Page 118
... DS41249D-page 116 Program STATUS Counter Register 000h 0001 1xxx 000h 000u uuuu 000h 0001 0uuu 000h 0000 uuuu uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu Preliminary © 2006 Microchip Technology Inc. PCON Register ---1 --0x ---u --uu ---u --uu ---u --uu ---u --uu ---1 --u0 ---u --uu ...
Page 119
... The GIE is cleared to disable any further interrupt • The return address is PUSHed onto the stack • The PC is loaded with 0004h © 2006 Microchip Technology Inc. PIC16F785/HV785 For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles ...
Page 120
... Sleep. See Section 15.6.1 “Wake-up from Sleep”. Preliminary 00h) in the TMR0 register will set by setting/clearing T0IE (1) Wake-up (If in Sleep mode) Interrupt to CPU © 2006 Microchip Technology Inc. ...
Page 121
... PEIE 0Ch PIR1 EEIF ADIF 8Ch PIE1 EEIE ADIE Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. © 2006 Microchip Technology Inc. PIC16F785/HV785 (1) (2) Interrupt Latency ...
Page 122
... STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into Status register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS41249D-page 120 Preliminary © 2006 Microchip Technology Inc. ...
Page 123
... Conditions WDTE = 0 CLRWDT command OSC FAIL detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP © 2006 Microchip Technology Inc. PIC16F785/HV785 15.5.2 WDT CONTROL The WDTE bit is located in the Configuration Word. When set, the WDT runs continuously. ...
Page 124
... WDTE FOSC2 Preliminary R/W-0 R/W-0 R/W-0 (1) bit 0 ( Bit is unknown Value on all Value on: Bit 1 Bit 0 other POR,BOR resets DC C 0001 1xxx 000q quuu WDTPS0 SWDTEN ---0 1000 ---0 1000 PS1 PS0 1111 1111 1111 1111 FOSC1 FOSC0 uuuu uuuu uuuu uuuu © 2006 Microchip Technology Inc. ...
Page 125
... Interrupt-on-change • External Interrupt from INT pin Other peripherals cannot generate interrupts since, during Sleep, no on-chip clocks are present. © 2006 Microchip Technology Inc. PIC16F785/HV785 When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to ...
Page 126
... Memory Programming Speci- fication” (DS41237). A typical In-Circuit Serial Programming connection is shown in Figure 15-11. Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h See the “PIC16F785/ IL IHH Programming Specification” © 2006 Microchip Technology Inc. ...
Page 127
... ICDCLK, ICDDATA Stack 1 level Data RAM 65h-70h, F0h Program Memory Address 0h must be NOP 700h-7FFh © 2006 Microchip Technology Inc. PIC16F785/HV785 For more information, see “MPLAB Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). FIGURE 15-12: 28-Pin PDIP SHNTREG ...
Page 128
... PIC16F785/HV785 16.0 VOLTAGE REGULATOR The PIC16HV785 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the V This eliminates the need for an external voltage regula- tor in systems sourced by an unregulated supply. All external devices connected directly to the V share the regulated supply voltage and contribute to ...
Page 129
... A read operation is always performed, even if the instruction is a Write command. © 2006 Microchip Technology Inc. PIC16F785/HV785 For example, a CLRF PORTA, clear all the data bits, then write the result back to PORTA ...
Page 130
... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2006 Microchip Technology Inc. ...
Page 131
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2006 Microchip Technology Inc. PIC16F785/HV785 ANDWF AND W with f Syntax: [label] ANDWF Operands Operation: (W) .AND. (f) ...
Page 132
... W register is cleared. Zero bit (Z) is set. Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. © 2006 Microchip Technology Inc. ...
Page 133
... If the result is ‘1’, the next instruc- tion is executed. If the result is ‘0’, then a NOP is executed instead, making it a two-cycle instruction. © 2006 Microchip Technology Inc. PIC16F785/HV785 GOTO Unconditional Branch Syntax: [ label ] ...
Page 134
... W register. The “don’t cares” will assemble as 0’s . Move label ] MOVWF 127 (W) (f) None 00 0000 1fff ffff Move data from W register to register ‘f’. No Operation [ label ] NOP None No operation None 00 0000 0xx0 0000 No operation. © 2006 Microchip Technology Inc. ...
Page 135
... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. © 2006 Microchip Technology Inc. PIC16F785/HV785 RLF Syntax: Operands: Operation: Status Affected: Encoding: 0000 1001 ...
Page 136
... Exclusive OR Literal with W [label] XORLW 255 (W) .XOR 1010 kkkk kkkk The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2006 Microchip Technology Inc. ...
Page 137
... Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’ the result is stored back in register ‘f’. © 2006 Microchip Technology Inc. PIC16F785/HV785 f,d dfff ffff Preliminary DS41249D-page 135 ...
Page 138
... PIC16F785/HV785 NOTES: DS41249D-page 136 Preliminary © 2006 Microchip Technology Inc. ...
Page 139
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC16F785/HV785 18.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 140
... MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an © 2006 Microchip Technology Inc. ...
Page 141
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. PIC16F785/HV785 18.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 142
... Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary © 2006 Microchip Technology Inc. ® L security ICs, CAN ® ...
Page 143
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to V © 2006 Microchip Technology Inc. PIC16F785/HV785 ................................................................................. -0. – ...
Page 144
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Frequency denotes system clock frequency. When using the HFINTOSC the system clock is after the postscaler. 3: The internal shunt regulator of the PIC16HV785 keeps V DS41249D-page 142 ( (2) Frequency (MHz below 5 ...
Page 145
... See Section 15.2.1 “Power-On Reset” for details. 0.05* — — V/ms See Section 15.2.1 “Power-On Reset” for details. — 2.1 — V can be lowered in Sleep mode without losing RAM data. for PIC16HV785 device (see Table 19-14). SHUNT Preliminary T +85°C for industrial A T +125°C for extended A Conditions 4 MHz: F ...
Page 146
... MHz OSC EC Oscillator mode kHz OSC INTRC mode MHz OSC INTOSC mode MHz OSC EXTRC mode MHz OSC HS Oscillator mode or I current from this limit. Max When A/D is off, it will not consume DD © 2006 Microchip Technology Inc. ...
Page 147
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V any current other than leakage current. the power-down current spec includes any such leakage from the A/D module. © 2006 Microchip Technology Inc. PIC16F785/HV785 (1), (2) Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 148
... MHz OSC EC Oscillator mode kHz OSC INTRC mode MHz OSC INTOSC mode MHz OSC EXTRC mode MHz OSC HS Oscillator mode or I current from this limit. Max When A/D is off, it will not DD © 2006 Microchip Technology Inc. ...
Page 149
... Sleep mode, with all I/O pins in high-impedance state and tied to V consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module. © 2006 Microchip Technology Inc. PIC16F785/HV785 Standard Operating Conditions (unless otherwise stated) ...
Page 150
... V SS PIN PIN XT, HS and SS PIN DD LP osc configuration 8 1.6 mA 4.5V (Ind 1.2 mA 4.5V (Ext -3 -1.3 mA 4.5V (Ind -1.0 mA 4.5V (Ext RB6 pin © 2006 Microchip Technology Inc. ...
Page 151
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 14.4.1 “Using the Data EEPROM” on page 105. © 2006 Microchip Technology Inc. PIC16F785/HV785 Standard Operating Conditions (unless otherwise stated) Operating temperature-40°C T +85° ...
Page 152
... for OSC2 output DS41249D-page 150 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance Load Condition Pin V SS Preliminary © 2006 Microchip Technology Inc. ...
Page 153
... All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. © 2006 Microchip Technology Inc. PIC16F785/HV785 Q1 ...
Page 154
... T — CY OSC Preliminary New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150 * ns 300 ns — ns — — ns — © 2006 Microchip Technology Inc. ...
Page 155
... FIGURE 19-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins © 2006 Microchip Technology Inc. PIC16F785/HV785 Freq. Min Typ† Max Tolerance 1% 7.92 8.00 8.08 (1) 2% 7.84 8.00 8.16 5% 7.60 8.00 8.40 — ...
Page 156
... TBD TBD TBD ms — — 2.0 s 2.025 — 2.175 V 100* — — s Preliminary © 2006 Microchip Technology Inc. (1) Conditions V = 5.0V, -40°C to +85°C DD Extended temperature V = 5.0V, -40°C to +85°C DD Extended temperature T = OSC1 period OSC V = 5.0V, -40°C to +85°C DD Extended Temperature V V (D005) ...
Page 157
... Delay from external clock edge to timer increment TMR * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. PIC16F785/HV785 ...
Page 158
... Typ† Max Units No Prescaler 0. With Prescaler 20 No Prescaler 0. With Prescaler — — Preliminary Conditions — — ns — — ns — — ns — — ns — — prescale value (1 © 2006 Microchip Technology Inc. ...
Page 159
... DD VR04 T Settling Time STABLE VR05 output current VROUT Legend: TBD = To Be Determined * These parameters are characterized but not tested. © 2006 Microchip Technology Inc. PIC16F785/HV785 Standard Operating Conditions (unless otherwise stated) Operating temperature Min Typ — — — ...
Page 160
... Comments V = 1.2V REF REF V = 0.5V REF REF V = 3.6V REF REF = 0V 50pF +125°C A Comments /2, Freq load Standard load ( connected Vss) © 2006 Microchip Technology Inc. ...
Page 161
... Dead Time Delay Characteristics Param Symbol Characteristics No. PW01* T Dead Time Delay DLY Legend: TBD = To Be Determined * These parameters are characterized but not tested. TABLE 19-14: SHUNT REGULATOR SPECIFICATIONS (PIC16HV785 only) SHUNT REGULATOR CHARACTERISTICS Param Symbol Characteristics No. SR01 V Shunt Voltage SHUNT SR02 I Shunt Current ...
Page 162
... V DD Preliminary Conditions = 5.0V (external) REF V = 5.0V (external) REF = 5.0V (external) REF = 5.0V (external) REF Absolute minimum to ensure 10-bit accuracy During V acquisition. AIN Based on differential HOLD V . AIN Transient during A/D conversion cycle. is allowed low as 1.0V. REF REF © 2006 Microchip Technology Inc. . ...
Page 163
... Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following T 2: See Section 12.2 “A/D Acquisition Requirements” for minimum conditions. © 2006 Microchip Technology Inc. PIC16F785/HV785 (1) /2) 131 130 ...
Page 164
... LSb (i.e., 4 4.096V) from the last sampled voltage (as stored HOLD If the A/D clock source is selected as RC, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed. © 2006 Microchip Technology Inc. ...
Page 165
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. © 2006 Microchip Technology Inc. PIC16F785/HV785 Preliminary DS41249D-page 163 ...
Page 166
... PIC16F785/HV785 NOTES: DS41249D-page 164 Preliminary © 2006 Microchip Technology Inc. ...
Page 167
... Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2006 Microchip Technology Inc. PIC16F785/HV785 Example PIC16F785-I/P ...
Page 168
... PIC16F785/HV785 Package Marking Information (Cont’d) 20-Lead QFN XXXXXXX XXXXXXX YWWNNN DS41249D-page 166 Example 16F785 -I/ML 0410017 Preliminary © 2006 Microchip Technology Inc. ...
Page 169
... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-019 © 2006 Microchip Technology Inc. PIC16F785/HV785 ...
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... E1 .291 .295 .299 D .496 .504 .512 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 Preliminary A2 MILLIMETERS MIN NOM MAX 20 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 12.60 12.80 13.00 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. © 2006 Microchip Technology Inc. ...
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... Foot Angle Lead Width B * Controlling Parameter Notes: Dimensions D and include mold flash or protrusions. Mold flash or protrusions shall not exceed 010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 © 2006 Microchip Technology Inc. PIC16F785/HV785 INCHES MILLIMETERS* ...
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... BSC E2 .102 .106 .110 D .157 BSC D2 .102 .106 .110 b .007 .010 .012 L .012 .016 .020 K .008 – – Preliminary BOTTOM VIEW MILLIMETERS* MIN NOM MAX 20 0.50 BSC 0.80 0.90 1.00 0.00 0.02 0.05 0.20 REF 4.00 BSC 2.60 2.70 2.80 4.00 BSC 2.60 2.70 2.80 0.18 0.25 0.30 0.30 0.40 0.50 0.20 – – Revised 09-12-05 © 2006 Microchip Technology Inc. ...
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... Updates throughout document. Revision C Revised part number to include “HV785”; Added PWM Setup Example; Added Voltage Regulator secton. Revision D Revised VROUT min./max. limits in Table 19-9. © 2006 Microchip Technology Inc. PIC16F785/HV785 APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from the PIC16F684 PICmicro device to the PIC16F785/HV785 ...
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... PIC16F785/HV785 NOTES: DS41249D-page 172 Preliminary © 2006 Microchip Technology Inc. ...
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... RA4 Pin....................................................................... 40 RA5 Pin....................................................................... 40 RB4 and RB5 Pins ...................................................... 43 RB6 Pin....................................................................... 43 RB7 Pin....................................................................... 43 RC0 and RC1 Pins...................................................... 43 RC0, RC6 and RC7 Pins ............................................ 46 RC1 Pin....................................................................... 46 © 2006 Microchip Technology Inc. PIC16F785/HV785 RC2 and RC3 Pins ..................................................... 47 RC4 Pin ...................................................................... 47 RC5 Pin ...................................................................... 48 Resonator Operation .................................................. 25 Timer1 ........................................................................ 51 Timer2 ........................................................................ 56 TMR0/WDT Prescaler ...
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... Data EEPROM Memory Write .................................. 104 Interrupt-on-change .................................................... 37 Oscillator Fail (OSF) ................................................... 31 PORTA Interrupt-on-change..................................... 118 RA2/INT .................................................................... 118 TMR0 ........................................................................ 118 TMR1 .......................................................................... 52 TMR2 to PR2 Match ............................................. 55, 56 INTOSC Specifications ..................................................... 150 IOCA (Interrupt-on-Change) ............................................... 37 IOCA Register..................................................................... 37 L Load Conditions................................................................ 148 Preliminary © 2006 Microchip Technology Inc ........................ 86 MPEDANCE ...
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... Pin Descriptions and Diagrams................................... 38 RA0 ............................................................................. 38 RA1 ............................................................................. 38 RA2 ............................................................................. 39 RA3 ............................................................................. 39 RA4 ............................................................................. 40 RA5 ............................................................................. 40 Specifications............................................................ 151 PORTB................................................................................ 42 Associated Registers .................................................. 44 Pin Descriptions and Diagrams................................... 43 RB4 ............................................................................. 43 © 2006 Microchip Technology Inc. PIC16F785/HV785 RB5............................................................................. 43 RB6............................................................................. 43 RB7............................................................................. 43 PORTC ............................................................................... 45 Associated Registers............................................ 33, 48 Pin Descriptions and Diagrams .................................. 46 RC0 ............................................................................ 46 RC1 ............................................................................ 46 RC2 ............................................................................ 47 RC3 ............................................................................ 47 RC4 ...
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... PWM Frequency ......................................................... 91 PWM Period................................................................ 91 PWM Phase................................................................ 91 PWM Phase resolution ............................................... 91 Shutdown.................................................................... 92 Two-Phase PWM Dead Time Delay ...................................................... 157 Two-Speed Clock Start-up Mode........................................ 30 V Voltage Reference (VR) Specifications ........................................................... 155 Voltage Reference Output (V Specifications ........................................................... 156 Voltage References ............................................................ 70 Associated Registers .................................................. 73 Preliminary © 2006 Microchip Technology Inc REF UFFER ...
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... Associated Registers ................................................ 122 Clock Source............................................................. 121 Modes ....................................................................... 121 Period........................................................................ 121 Specifications............................................................ 152 WDTCON Register ........................................................... 122 WPUA (Weak Pull-up PORTA) ........................................... 36 WPUA Register ................................................................... 36 WWW Address.................................................................. 175 WWW, On-Line Support ....................................................... 4 X XORLW Instruction ........................................................... 134 XORWF Instruction ........................................................... 134 © 2006 Microchip Technology Inc. PIC16F785/HV785 Preliminary DS41249D-page 177 ...
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... PIC16F785/HV785 NOTES: DS41249D-page 178 Preliminary © 2006 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. PIC16F785/HV785 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41249D-page 180 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41249D Preliminary © 2006 Microchip Technology Inc. ...
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... TQFP (Thin Quad Flatpack PLCC SO = SOIC SP = Skinny Plastic DIP P = PDIP Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) © 2006 Microchip Technology Inc. PIC16F785/HV785 XXX Examples: Pattern a) PIC18LF258 - I/L 301 = Industrial temp., PLCC package, Extended V #301. b) PIC18LF458 - I/PT = Industrial temp., TQFP package, Extended V (1) (2) , PIC18F248/258T , c) PIC18F258 - E/L = Extended temp ...
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... Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...