PIC16F883 Microchip Technology Inc., PIC16F883 Datasheet - Page 33

• Manufacturer Part Number: PIC16F883
• Description: 28/40/44-pin Flash-based, 8-bit Cmos Microcontrollers With Nanowatt Technology
• Manufacturer: Microchip Technology Inc.

2.2.2.3
The INTCON register, shown in Register 2-3, is a
readable and writable register, which contains the various
enable and flag bits for TMR0 register overflow, PORTB
change and external INT pin interrupts.
REGISTER 2-3:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
GIE
2:
3:
IOCB register must also be enabled.
T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
Includes ULPWU interrupt.
INTCON Register
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
RBIE: PORTB Change Interrupt Enable bit
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
T0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in
0 = None of the PORTB general purpose I/O pins have changed state
R/W-0
PEIE
software)
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
T0IE
PIC16F882/883/884/886/887
R/W-0
INTE
Preliminary
(2)
(1,3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RBIE
R/W-0
Note:
(1,3)
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
T0IF
R/W-0
(2)
software
x = Bit is unknown
R/W-0
INTF
should
DS41291D-page 31
ensure
R/W-x
RBIF
bit 0
the