ADC12034 National Semiconductor Corporation, ADC12034 Datasheet - Page 4

• Manufacturer Part Number: ADC12034
• Description: Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
• Manufacturer: National Semiconductor Corporation

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Pin Descriptions
CCLK
SCLK
DI
DO
EOC
CS
The clock applied to this input con-
trols the successive approximation
conversion time interval and the ac-
quisition time. The rise and fall times
of the clock edges should not exceed
1 µs.
This is the serial data clock input.
The clock applied to this input con-
trols the rate at which the serial data
exchange occurs. The rising edge
loads the information on the DI pin
into the multiplexer address and
mode select shift register. This ad-
dress controls which channel of the
analog input multiplexer (MUX) is
selected and the mode of operation
for the A/D. With CS low the falling
edge of SCLK shifts the data result-
ing from the previous ADC conver-
sion out on DO, with the exception of
the first bit of data. When CS is low
continuously, the first bit of the data
is clocked out on the rising edge of
EOC (end of conversion). When CS
is toggled the falling edge of CS al-
ways clocks out the first bit of data.
CS should be brought low when
SCLK is low. The rise and fall times
of the clock edges should not exceed
1 µs.
This is the serial data input pin. The
data applied to this pin is shifted by
the rising edge of SCLK into the mul-
tiplexer address and mode select
register. Table 2 through Table 5
show the assignment of the multi-
plexer address and the mode select
data.
The data output pin. This pin is an
active push/pull output when CS is
low. When CS is high, this output is
TRI-STATE
result (D0–D12) and converter sta-
tus data are clocked out by the falling
edge of SCLK on this pin. The word
length and format of this result can
vary (see Table 1). The word length
and format are controlled by the data
shifted into the multiplexer address
and mode select register (see Table
5).
This pin is an active push/pull output
and indicates the status of the
ADC12030/2/4/8. When low, it sig-
nals that the A/D is busy with a con-
version, auto-calibration, auto-zero
or power down cycle. The rising
edge of EOC signals the end of one
of these cycles.
This is the chip select pin. When a
logic low is applied to this pin, the
rising edge of SCLK shifts the data
on DI into the address register. This
low also brings DO out of TRI-
®
. The A/D conversion
4
DOR
CONV
PD
STATE. With CS low the falling edge
of SCLK shifts the data resulting
from the previous ADC conversion
out on DO, with the exception of the
first bit of data. When CS is low con-
tinuously, the first bit of the data is
clocked out on the rising edge of
EOC (end of conversion). When CS
is toggled the falling edge of CS al-
ways clocks out the first bit of data.
CS should be brought low when
SCLK is low. The falling edge of CS
resets a conversion in progress and
starts the sequence for a new con-
version. When CS is brought back
low during a conversion, that con-
version is prematurely terminated.
The data in the output latches may
be corrupted. Therefore, when CS is
brought back low during a conver-
sion in progress the data output at
that time should be ignored. CS may
also be left continuously low. In this
case it is imperative that the correct
number of SCLK pulses be applied
to the ADC in order to remain syn-
chronous. After the ADC supply
power is applied it expects to see 13
clock pulses for each I/O sequence.
The number of clock pulses the ADC
expects is the same as the digital
output word length. This word length
can be modified by the data shifted
in on the DO pin. Table 5 details the
data required.
This is the data output ready pin.
This pin is an active push/pull output.
It is low when the conversion result
is being shifted out and goes high to
signal that all the data has been shift-
ed out.
A logic low is required on this pin to
program any mode or change the
ADC's configuration as listed in the
Mode Programming Table 5 such as
12-bit conversion, 8-bit conversion,
Auto-Cal, Auto Zero etc. When this
pin is high the ADC is placed in the
read data only mode. While in the
read data only mode, bringing CS
low and pulsing SCLK will only clock
out on DO any data stored in the AD-
Cs output shift register. The data on
DI will be neglected. A new conver-
sion will not be started and the ADC
will remain in the mode and/or con-
figuration previously programmed.
Read data only cannot be performed
while a conversion, Auto-Cal or Au-
to-Zero are in progress.
This is the power down pin. When
PD is high the A/D is powered down;
when PD is low the A/D is powered
up. The A/D takes a maximum of 250
µs to power up after the command is
given.