MPC857T Freescale Semiconductor, Inc, MPC857T Datasheet - Page 53

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MPC857T

Manufacturer Part Number
MPC857T
Description
Mpc857t Powerquicc Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
1
2
3
4
(FE=0, CE=0)
(FE=1, CE=1)
Num
83a
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
L1RSYNC
84
85
86
87
88
L1ST(4-1)
L1RCLK
L1RCLK
(Output)
L1RXD
(Input)
(Input)
(Input)
(Input)
L1RCLK, L1TCLK width high (DSC = 1)
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC
L1GR setup time
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT =
0, DSC = 0)
Figure 52. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
73
71
2
Characteristic
76
75
74
Table 19. SI Timing (continued)
72
70
BIT0
3
RFSD=1
4
78
77
71a
P + 10
42.00
42.00
1.00
Min
All Frequencies
79
CPM Electrical Characteristics
30.00
Max
0.00
L1TCL
Unit
ns
ns
ns
ns
ns
K
53

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