ATA5723 ATMEL Corporation, ATA5723 Datasheet - Page 20

• Manufacturer Part Number: ATA5723
• Description: Ata5723 Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

20
ATA5723/ATA5724/ATA5728
Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recom-
mended. If the bit check is set to 0 or the receiver is set to receiving mode using the pin
POLLING/_ON, the data clock is available if the data clock control logic has detected the dis-
tance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-1.
Figure 9-2.
Data_out (DATA)
Data_out (DATA)
DATA_CLK
DATA_CLK
Dem_out
Dem_out
Timing Diagram of the Data Clock
Data Clock Disappears Because of a Timing Error
'1'
'1'
Bit-check mode
data clock control
Timing error
Receiving mode,
Bit check ok
logic active
'1'
'1'
'1'
'1'
Preburst
T
ee
'1'
'1'
T
ee
< T
T
'1'
'1'
Lim_min
2T
Start bit
or T
'0'
'0'
Data
Receiving mode,
Lim_max
bit check active
data clock control logic active
'1'
'1'
< T
Receiving mode,
ee
'1'
'1'
< T
t
Lim_min_2T
Delay
'0'
'0'
Data
or T
'1'
'1'
ee
9106D–RKE–02/08
t
> T
P_Data_Clk
Lim_max_2T
'0'
'0'