ADIS16060 Analog Devices, Inc., ADIS16060 Datasheet - Page 11

• Manufacturer Part Number: ADIS16060
• Description: Wide Bandwidth Yaw Rate Gyroscope With Spi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
BASIC OPERATION
The ADIS16060 is designed for simple integration into indus-
trial system designs, requiring only a 5.0 V power supply, two
mode select lines and three serial communications lines. The
SPI handles all digital I/O communication in the ADIS16060.
SERIAL PERIPHERAL INTERFACE (SPI)
The ADIS16060 SPI port includes five signals: master select 1
( MSEL1 ), master select 2 ( MSEL2 ), serial clock (SCLK), data
input (DIN), and data output (DOUT). The MSEL1 line is used
when reading data out of the sensor (DOUT) and the MSEL2
line is used when configuring the sensor (DIN).
Selecting Output Data
Refer to Table 5 to determine the appropriate DIN bit sequence
based on the required data source. Table 2 and Figure 3 provide
the necessary timing details for the input configuration
sequence. Once the MSEL2 goes high, the last eight, DIN bits
are loaded into the internal control register, which represents
DB0-DB7 in Table 5.
Table 5. DIN Configuration Bit Assignments
Action
Measure Angular Rate (Gyro)
Measure Temperature
Measure AIN2
Measure AIN1
Set Positive Self-Test
Set Negative Self-Test
DB7
X
X
0
0
1
0
DB6
Rev. PrB | Page 11 of 16
0
1
X
X
0
0
DB5
1
0
0
0
X
X
Output Data Access
Use Table 2 and Figure 2 to determine the appropriate timing
considerations for reading output data.
OUTPUT DATA FORMATTING
All of the output data is in an offset-binary format, which in
this case, means that the ideal output for a zero rate condition
is 8192 codes. If the sensitivity is equal to 0.0121°/s/LSB,
then a rate of +10°/s results in a change of 826 codes, and a
digital rate output of +9018 codes. If an offset error of −20°/s
is introduced, this reduces the output by 1653 codes (typical
sensitivity assumed), resulting in a digital rate output of 7365
codes.
ADC CONVERSION
The internal, successive approximation ADC begins the conversion
process on the falling edge of MSEL1 and begins to place data,
MSB-first, on the DOUT line, on the 6
shown in Figure 2. The entire conversion process takes 22 SCLK
cycles. Once MSEL1 goes high, the acquisition process starts, in
preparation for the next conversion cycle.
DB4
0
1
0
0
X
X
DB3
0
0
0
0
0
0
DB2
0
0
0
0
0
0
th
falling edge of SCLK, as
DB1
0
0
0
0
0
1
ADIS16060
DB0
0
0
0
0
1
0