ADP3212 ON Semiconductor, ADP3212 Datasheet
ADP3212
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ADP3212 Summary of contents
Page 1
... Intel processors. An internal 7-bit DAC is used to read a VID code directly from the processor and to set the CPU core voltage to a value within the range of 0 1.5 V. The ADP3212/NCP3218 is programmable for 1-, 2-, or 3-phase operation. The output signals ensure interleaved 2- or 3-phase operation. ...
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... ADP3212/NCP3218 TRDET TRDET COMP FB REF LLINE SWFB1 SWFB2 SWFB3 PH0 PH1 DAC + 200mV CSREF DAC - 300mV PWRGD CLKEN CLKEN FBRTN FUNCTIONAL BLOCK DIAGRAM GND VCC EN RPM RT RAMP UVLO UVLO TRDET TRDET Oscillator Shutdown Shutdown Generator Generator and Bias and Bias VEA ...
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... Power MOSFETs .........................................................................32 Ramp Resistor Selection.............................................................33 Current Limit Setpoint...............................................................33 Current Monitor..........................................................................33 Feedback Loop Compensation Design ....................................33 C Selection and Input Current di/dt Reduction .................. Snubber..................................................................................35 Selecting Thermal Monitor Components................................35 Tuning Procedure for ADP3212/NCP3218.............................36 Layout and Component Placement ..........................................37 Outline Dimension .........................................................................39 Ordering Guide ...........................................................................41 Rev. SpA | Page ...
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... ADP3212/NCP3218 SPECIFICATIONS VCC = PVCC = 5V, FBRTN = PGND = GND = 5V VARFREQ = H, DPRSLP = L, PSI = 1. 1.2000 −40°C to 100°C, unless otherwise noted. A Table 1. Parameter Symbol VOLTAGE CONTROL VOLTAGE ERROR AMPLIFIER (VEAMP) 2 FB, LLINE Voltage Range FB, LLINE Offset Voltage ...
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... Measured from CSCOMP to CSREF, R 3-ph configuration, PSI = H 3-ph configuration, PSI = L 2-ph configuration, PSI = H 2-ph configuration, PSI = L 1-ph configuration Measured from OCP event to PWRGD de-assertion Measured from ILIM to IMON LIM = −20 μA I LIM = −10 μA I LIM Rev. SpA | Page ADP3212/NCP3218 Min Typ Max 1.5 1.55 1.6 1.3 1.35 1.4 −370 −300 −75 −10 85 250 ...
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... ADP3212/NCP3218 Parameter Symbol IMON Clamp Voltage V MAXMON PULSE WIDTH MODULATOR CLOCK OSCILLATOR RT Voltage V RT PWM Clock Frequency f CLK 2 Range PWM Clock Frequency f CLK RAMP GENERATOR RAMP Voltage V RAMP 2 RAMP Current Range I RAMP PWM COMPARATOR 2 PWM Comparator Offset V OSRPM RPM COMPARATOR RPM Current ...
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... VRTT(SOURCE high VCC is rising VCC is falling BST = PVCC BST = PVCC BST = PVCC nF, Figure 2 L BST = PVCC nF, Figure 2 L BST = PVCC, Figure 2 DRVH Rev. SpA | Page ADP3212/NCP3218 Min Typ Max Units μA −1 μA 1 200 ns 0 μ ...
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... ADP3212/NCP3218 Parameter Symbol BST Quiescent Current LOW-SIDE MOSFET DRIVER Pull-up Resistance, Sourcing 3 Current Pull-down Resistance, 3 Sinking Current Transition Times tr DRVL tf DRVL Propagation Delay Times tpdh SW Transition Timeout t TOSW SW Off Threshold V OFFSW PVCC Quiescent Current BOOTSTRAP RECTIFIER SWITCH 3 On Resistance 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). ...
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... TIMING DIAGRAM Timing is referenced to the 90% and 10% points, unless otherwise noted. IN tpdl DRVL DRVL DRVH (WITH RESPECT TO SW DRVL tpdh tr DRVH DRVH V TH Figure 2. Timing Diagram Rev. SpA | Page ADP3212/NCP3218 tpdl tr DRVH DRVL tf DRVH V TH tpdh DRVL 1V ...
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... ADP3212/NCP3218 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC, PVCC1, PVCC2 FBRTN, PGND1, PGND2 BST1, BST2, DRVH1, DRVH2 DC t < 200 ns BST1 to PVCC, BST2 to PVCC DC t < 200 ns BST1 to SW1, BST2 to SW2 SW1, SW2 DC t < 200 ns DRVH1 to SW1, DRVH2 to SW2, DRVL1 to PGND1, DRVL2 to PGND2 DC t < 200 ns ...
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... RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn-on threshold voltage. Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device when operating in multiphase PWM mode.threshold of the converter. Rev. SpA | Page ADP3212/NCP3218 ...
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... Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for multiphase configuration. Deeper Sleep Control Input. Power State Indicator Input. Pulling this pin to GND forces the ADP3212/NCP3218 to operate in single-phase mode. Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation voltage from 0 ...
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... TEST CIRCUITS Figure 4. Closed-Loop Output Voltage Accuracy ADP3212 5V VCC 37 CSCOMP 20 100nF 39kΩ CSSUM 19 1kΩ CSREF 18 1.0V GND Figure 5. Current Sense Amplifier CSCOMP – 40V OS Rev. SpA | Page ADP3212/NCP3218 Figure 6. Positioning Accuracy ...
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... ADP3212/NCP3218 TYPICAL PERFORMANCE CHARACTERISTICS 20°C to 100°C, unless otherwise noted. VID A 400 350 VARFREQ = 0V 300 250 200 VARFREQ = 5V 150 100 50 0 0.25 0.5 0.75 1 VID OUTPUT VOLTAGE (V) Figure 7. Switching Frequency vs. VID Output Voltage in PWM Mode 1000 RT = 187kΩ 2 Phase Mode 100 1.25 1.5 10 Figure 8. Per Phase Switching Frequency vs. RT Resistance Rev ...
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... COMP pin voltage rises to a voltage limit set by the VID voltage and an external resistor connected between the RPM pin and GND. In RPM mode, the ADP3212/NCP3218 turns off the low-side (synchronous rectifier) MOSFET when the inductor current drops to 0. Turning off the low-side ...
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... The ADP3212/NCP3218 can be used to power IMVP-6.5 GMCH. To configure the ADP3212/NCP3218 in GPU, connect PH1 to VCC and connect PH0 to GND. In GPU mode, the ADP3212/NCP3218 operates in single phase only. In GPU mode, the boot voltage is disabled. During start up, the output voltage ramps up to the programmed VID voltage. There is no other difference between GPU mode and normal CPU mode ...
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... Selected by 2 the User Current Limit * Yes N [3 Yes * Figure 9. Single-Phase RPM Mode Operation ADP3212/NCP3218 No. of Phases in Operation 3 Operation Modes N PWM, CCM only N PWM, CCM only 1 PWM, CCM only N PWM, CCM only 1 RPM, automatic CCM/DCM 1 PWM, CCM only ...
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... ADP3212/NCP3218 RAMP Clock Oscillator 0. RAMP Clock Oscillator 0. RAMP Clock Oscillator 0.2V VCC RAMP + - COMP Gate Driver BST1 BST DRVH1 Flip-Flop DRVH SW1 ...
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... Setting Switch Frequency Master Clock Frequency in PWM Mode When the ADP3212/NCP3218 runs in PWM, the clock frequency is set by an external resistor connected from the RT pin to GND. The frequency is constant at a given VID code but varies with the VID voltage: the lower the VID voltage, the lower the clock frequency ...
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... Active Impedance Control Mode section. The magnitude of the internal ramp can be set so that the transient response of the system is optimal. The ADP3212/NCP3218 monitors the supply voltage to achieve feedforward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMP pin determines the slope of the internal PWM ramp ...
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... The change can be either upwards or downwards steps. ADP3212/NCP3218 When a VID input changes, the ADP3212/NCP3218 detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7-bit VID input code is in transition ...
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... FETs are off and no current flows into the inductor (see Figure 17). Figure 18 shows the inductor current and switch node voltage in DCM. In DCM with a light load, the ADP3212/NCP3218 monitors the switch node voltage to determine when to turn off the low-side FET. Figure 19 shows a typical waveform in DCM with load current ...
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... INPUT 250 19V INPUT 200 150 100 LOAD CURRENT (A) Figure 20. Single-Phase CCM/DCM Frequency vs. Load Current 12 14 Rev. SpA | Page ADP3212/NCP3218 ...
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... SS and PGDELAY pins to ground, and drives the DRVH and DRVL outputs low. The user must adhere to proper power-supply sequencing during startup and shutdown of the ADP3212/NCP3218. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off ...
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... 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 V 1 ADP3212/NCP3218 VID5 VID4 VID3 VID2 VID1 VID0 ...
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... ADP3212/NCP3218 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 0 0.0750 0.0625 0.0500 0.0375 0.0250 ...
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... Figure 21. Typical Dual-Phase Application Circuit Rev. SpA | Page ADP3212/NCP3218 ...
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... SW SETTING THE SWITCHING FREQUENCY FOR RPM OPERATION OF PHASE 1 During the RPM operation of Phase 1, the ADP3212/NCP3218 ) = 1.05 V runs in pseudoconstant frequency if the load current is high enough for continuous current mode. While in DCM, the switching frequency is reduced with the load current in a linear ) = 0.9512 V OFL manner ...
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... CS change in resistance, it cancels the temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, series resistors R the NTC and produce the desired temperature coefficient tracking Rev. SpA | Page ADP3212/NCP3218 (summer) and resistors R and C (filters). The output × ...
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... ADP3212/NCP3218 Figure 22. Temperature-Compensation Circuit Values The following procedure and expressions yield values for and R (the thermistor value at 25°C) for a given CS1 CS2 TH R value Select an NTC to be used based on its type and value. Because the value needed is not yet determined, start with a thermistor with a value close to R initial tolerance of better than 5% ...
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... X For this multimode control technique, an all ceramic capacitor . If the C is greater X(MIN) design can be used if the conditions of Equations 11, 12, and 13 are satisfied. Rev. SpA | Page ADP3212/NCP3218 ⎛ ⎜ ⎜ × 330 ⎜ ...
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... MOSFETs must be used. The maximum output current determines the R O requirement for the low-side (synchronous) MOSFETs. In the ADP3212/NCP3218, currents are balanced between phases; the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (n ). With conduction losses SF ...
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... LIM When the ADP3212/NCP3218 is configured for 3 phase operation, the equation above is used to set the current limit. When the ADP3212/NCP3218 switches from 3 phase to 1 phase operation by PSI or DPRSLP signal, the current is single phase (18) is one third of the current limit in 3 phase. ...
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... A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 23 shows the Type III amplifier used in the ADP3212/NCP3218. Figure 24 shows the locations of the two poles and two zeros created by this amplifier. Figure 23. Voltage Error Amplifier Figure 24 ...
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... VRTT signal is asserted. The following calculation sets the alarm temperature: R where V Because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mV. Assuming the same Rev. SpA | Page ADP3212/NCP3218 1 = π × × × ...
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... Build a circuit based on the compensation values computed from the design spreadsheet. 2. Connect a dc load to the circuit. 3. Turn on the ADP3212/NCP3218 and verify that it operates properly. 4. Check for jitter with no load and full load conditions. Set the DC Load Line 1. Measure the output voltage with no load (V that this voltage is within the specified tolerance range ...
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... If critical signal lines (including the output voltage sense by 25%. A lines of the ADP3212/NCP3218) must cross through power circuitry best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise ...
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... Kelvin connected to the center point of the copper bar, which is the V inductors of all the phases the back of the ADP3212/NCP3218 package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the ADP3212/NCP3218 is not recommended because the metal pad may cause shorting between vias ...
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... OUTLINE DIMENSION Figure 30. NCP3218 48-Lead Lead Frame Chip Scale Package [QFN_VQ × Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters Rev. SpA | Page ADP3212/NCP3218 ...
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... ADP3212/NCP3218 Figure 31. ADP3212 48-Lead Lead Frame Chip Scale Package [QFN_VQ × Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters Rev. SpA | Page ...
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... Lead Frame Chip Scale Package [QFN_VQ] 7x7 mm, 0.5 mm pitch 48-Lead Lead Frame Chip Scale Package [QFN_VQ] 6x6 mm, 0.4 mm pitch Rev. SpA | Page ADP3212/NCP3218 Package Package Marking Ordering Option Quantity CP-48-1 Line 1: ADP3212 2,500 Line 2: AWLYYWWG CP-48-1 Line 1: NCP3218 2,500 Line 2: AWLYYWWG ...
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... ADP3212/NCP3218 NOTES Rev. SpA | Page ...
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... NOTES ADP3212/NCP3218 Rev. SpA | Page ...