HV9912 Supertex, Inc., HV9912 Datasheet - Page 7

• Manufacturer Part Number: HV9912
• Description: Switch-mode Led Driver Ic With High Current Accuracy And Hiccup Mode Protection
• Manufacturer: Supertex, Inc.

Slope Compensation
For continuous conduction mode converters operating in the
constant frequency mode, slope compensation becomes
necessary to ensure stability of the peak current mode con-
troller, if the operating duty cycle is greater than 0.5. Choos-
ing a slope compensation which is one half of the down
slope of the inductor current ensures that the converter will
be stable for all duty cycles.
Slope compensation can be programmed by two resistors
R
inductor current, the slope compensation resistors can be
computed as:
where R
switching FET current.
Note: The maximum current that can be sourced out of the
SC pin is limited to 100µA. This limits the minimum value of
the R
pensation produces a value of R
then R
mended that R
Current Sense
The current sense input of the HV9912 includes a built in
100ns (minimum) blanking time to prevent spurious turn off
due to the initial current spike when the FET turns on.
The HV9912 includes two high-speed comparators - one is
used during normal operation and the other is used to limit
the maximum input current during input under voltage or
overload conditions.
The IC includes an internal resistor divider network, which
steps down the voltage at the COMP pin by a factor of 15.
This stepped-down voltage is given to one of the compara-
tors as the current reference. The reference to the other
comparator, which acts to limit the maximum inductor cur-
rent, is given externally.
It is recommended that the sense resistor R
as to provide about 250mV current sense signal.
Current Limit
Current limit has to be set by a resistor divider from the
1.25V reference available on the IC. Assuming a maximum
operating inductor current I
the maximum voltage at the CLIM pin can be set as:
SLOPE
SLOPE
and R
SC
CS
would have to be reduced accordingly. It is recom-
resistor to 25kΩ. If the equation for slope com-
R
is the current sense resistor which senses the
V
SC
SC
CLIM
. Assuming a down slope of DS (A/µs) for the
SLOPE
= R
≥ 1.2 x I
SLOPE
be chosen in the range of 25kΩ - 50kΩ.
x DS x 10
PK
x R
PK
(including the ripple current),
10
CS
+ 5 x R
SLOPE
6
x T
R
SLOPE
S
less than this value,
x R
CS
x 0.9
CS
CS
be chosen so
(Eqn. 4)
(Eqn. 5)
7
Note that this equation assumes a current limit at 120%
of the maximum input current. Also, if V
450mV, the saturation of the internal opamp will determine
the limit on the input current rather than the CLIM pin. In
such a case, the sense resistor R
V
It is recommended that no capacitor be connected between
CLIM and GND.
Internal 1MHz Transconductance Amplifi er
HV9912 includes a built in 1MHz transconductance ampli-
fi er, with tri-state output, which can be used to close the
feedback loop. The output current sense signal is connected
to the FDBK pin and the current reference is connected to
the IREF pin.
The output of the opamp is controlled by the signal applied
to the PWMD pin. When PWMD is high, the output of the
opamp is connected to the COMP pin. When PWMD is low,
the output is left open. This enables the integrating capacitor
to hold the charge when the PWMD signal has turned off the
gate drive. When the IC is enabled, the voltage on the inte-
grating capacitor will force the converter into steady state
almost instantaneously.
The output of the opamp is buffered and connected to the
current sense comparator using a 15:1 divider. The buffer
helps to prevent the integrator capacitor from discharging
during the PWM dimming state.
PWM Dimming
PWM dimming can be achieved by driving the PWMD pin
with a TTL compatible square wave source. The PWM sig-
nal is connected internally to the three different nodes - the
transconductance amplifi er, the FLT output and the GATE
output.
When the PWMD signal is high, the GATE and FLT pins
are enabled and the output of the transconductance opamp
is connected to the external compensation network. Thus,
the internal amplifi er controls the output current. When the
PWMD signal goes low, the output of the transconductance
amplifi er is disconnected from the compensation network.
Thus, the integrating capacitor maintains the voltage across
it. The GATE is disabled, so the converter stops switching
and the FLT pin goes low, turning off the disconnect switch.
The output capacitor of the converter determines the PWM
dimming response of the converter, since it has to get
charged and discharged whenever the PWMD signal goes
high or low. In the case of a buck converter, since the in-
ductor current is continuous, a very small capacitor is used
across the LEDs. This minimizes the effect of the capacitor
on the PWM dimming response of the converter. However,
in the case of a boost converter, the output current is dis-
CLIM
reduces below 550mV.
CS
should be reduced till
CLIM
Preliminary
is greater than
HV9912