HV9112 Supertex, Inc., HV9112 Datasheet - Page 6

• Manufacturer Part Number: HV9112
• Description: High-voltage Current-mode Pwm Controller
• Manufacturer: Supertex, Inc.

Test Circuits
Detailed Description
Preregulator
The preregulator/startup circuit for the HV9112 consists of
a high-voltage n-channel depletion-mode DMOS transis-
tor driven by an error amplifi er to form a variable current
path between the VIN terminal and the VDD terminal. The
maximum current (about 20 mA) occurs when V
current reducing as V
when V
if V
supply the chip is controlling). No current other than leakage
is drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
C
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable.
A common resistor divider string is used to monitor V
both the under voltage lockout circuit and the shutoff circuit
of the high voltage FET. Setting the under voltage sense
point about 0.6V lower on the string than the FET shutoff
point guarantees that the under voltage lockout always re-
leases before the FET shuts off.
STORAGE
DD
+10V
(V
is held at 10 or 12V by an external source(generally the
(–V
NOTE: Set Feedback Voltage so that
GND
DD
DD
(FB)
IN
)
≥ 100 x (gate charge of FET at 10V ÷ 10V)
)
rises to somewhere between 7.8 and 9.4V, so that
V
COMP
Reference
= V
0.1µF
DD
DIVIDE
rises. This path shuts off altogether
Error Amp Z
+
–
± 1mV before connecting transformer
1.0V swept 100Hz – 2.2MHz
V
1
OUT
secondary)
Tektronix
P6021
(1 turn
DD
= 0, with
V
2
DD
60.4K
40.2K
for
6
Bias Circuit
An external bias resistor, connected between the BIAS pin
and VSS is required by the HV9112 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. The nominal external bias current requirement is 15 to
20µA, which can be set by a 390KΩ to 510KΩ resistor if a
10V V
12V. A precision resistor is not required; ± 5% is fi ne.
Clock Oscillator
The clock oscillator of the HV9112 consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and,
in the 50% maximum duty cycle versions, a frequency divid-
ing fl ip-fl op. A single external resistor between the OSC IN
and OSC OUT is required to set the oscillator frequency (see
graph). For the 50% maximum duty cycle versions the Dis-
charge pin is internally connected to GND. For the 99% duty
cycle version, the Discharge pin can either be connected to
VSS directly or connected to VSS through a resistor used
to set a deadtime. One major difference exists between the
Supertex HV9112 and competitive 9110’s. On the Supertex
part, the oscillator is shut off when a shutoff command is re-
ceived. This saves about 150µA of quiescent current, which
aids in the construction of power supplies that meet CCITT
specifi cation I-430, and in other situations where an abso-
lute minimum of quiescent power dissipation is required.
DD
0.1V swept 10Hz – 1MHz
is used, or a 510kΩ to 680KΩ resistor if V
10.0V
4.00V
Reference
100K1%
0.1µF
PSRR
+
–
100K1%
V
2
HV9112
DD
V
1
will be