S1M8837 Samsung Semiconductor, Inc., S1M8837 Datasheet - Page 5

• Manufacturer Part Number: S1M8837
• Description: Fractional-n Rf/integer-n If Dual Pll
• Manufacturer: Samsung Semiconductor, Inc.

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
PIN DESCRIPTION
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
Symbol
V
GNDRF
CLOCK
CPoRF
RF_EN
V
GNDIF
DGND
OSCin
DGND
IF_EN
CPoIF
DATA
V
OUT1
OUT0
VpRF
finRF
finRF
DD
foLD
VpIF
finIF
finIF
DD
DD
LE
RFa
RF
IF
I/O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
I
I
I
I
I
I
I
I
I
I
RF PLL power supply (2.7V to 4.0V). Must be equal to V
Power supply for RF charge pump. Must be
RF charge pump output. Connected to an external loop filter.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the external VCO.
RF prescaler complementary input. For a single-ended output RF VCO, a bypass
capacitor should be placed as close as possible to this pin and be connected
directly to the ground plane.
Ground for RF PLL analog circuitry.
PLL power supply (2.7V to 4.0V) for RF analog (prescaler). Must be equal to V
Oscillator input to drive both the IF and RF R counter inputs.
Multiplexed output of N or R divider and RF/IF lock detect.
RF PLL Enable (Enable when HIGH, Power down when LOW). Controls the RF PLL
to power down directly, not depending on a program control. Also sets the charge
pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on
the state of RF_CTL_WORD.
IF PLL Enable (Enable when HIGH, Power-down when LOW). Controls the IF PLL
to power down directly. The same as RF_EN except that power-up depends on the
state of IF_CTL_WORD.
CMOS clock input. Data for the various counters is clocked into the 22-bit shift
register on the rising edge.
Binary serial data input. Data entered MSB (Most Significant Bit) first.
Load enable when LE goes HIGH. High impedance CMOS input.
Ground for IF analog circuitry.
IF prescaler complementary input. For a single-ended output IF VCO, a bypass
capacitor should be placed as close as possible to this pin.
IF prescaler input. Small signal input from the VCO.
Ground for IF PLL digital circuitry.
IF charge pump output. Connected to an external loop filter.
Power supply for IF charge pump. Must be
IF PLL power supply (2.7V to 4.0V). Must be equal to V
Programmable CMOS output. Level of the output is controlled by W2[19] bit.
Programmable CMOS output. Level of the output is controlled by W2[18] bit.
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous
switches between active low and tri-state.
Descriptions
V
V
DD
DD
RF and V
RF and V
DD
DD
RF.
IF.
DD
DD
IF.
IF.
S1M8836/37
DD
RF
5