S1D15715 Epson Electronics America, Inc., S1D15715 Datasheet - Page 25

• Manufacturer Part Number: S1D15715
• Description: Liquid Crystal Display =lcd Driver
• Manufacturer: Epson Electronics America, Inc.

6.4 Display Timing Generator Circuit
The display timing generator circuit generates the timing signal from the display clocks to the line address
circuit and the display data latch circuit. Since the read out of the displayed data to the LCD driver circuit is
independent from access to the display data RAM from MPU, accessing the display data RAM asynchronously
during liquid crystal display will not negatively affect the display such as flickering.
The display timing generator circuit also generates common timing signal and liquid crystal alternating signal
from the display clocks. Normally, LCD waveform generates dual-frame driver waveform. However, by
setting the data (n-1) to the n-line inversion drive register, n-line inversion driver waveform can be generated.
When problem in display quality such as crosstalk exists, it can be solved by using the n-line inversion driver
waveform. The number of the lines n to be alternated shall be determined by actually displaying on the LCD.
Dual-frame driver waveform (example of S1D15715 1/17Duty)
Rev.1.0
CL
Frame
alternating
COM 0
COM 1
RAM
DATA
SEG n
16 17
1
2
3
4
5
6
EPSON
Fig.6
12 13 14 15 16 17
S1D15715 Series Technical Manual
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V
V
V
V
V
V
V
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0
1
4
SS
0
1
4
SS
0
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SS