CE71 Fujitsu Microelectronics, Inc., CE71 Datasheet - Page 2

• Manufacturer Part Number: CE71
• Description: 0.25um Cmos Technology
• Manufacturer: Fujitsu Microelectronics, Inc.

CE71 Series Embedded Array
Mixed-Signal Macros
D/A Converters
• 10-bit: 1 MS/s, 1.5 MS/s,
• 8-bit: 200 KS/s, 1 MS/s, 50 MS/s
A/D Converters
• 12-bit: 1 MS/s
• 10-bit: 1 MS/s, 20 MS/s, 40 MS/s
• 8-bit: 1 MS/s, 30 MS/s, 50 MS/s
• 6-bit: 100 MS/s, 500 MS/s
Multiplier Compiler
• Multiplicand (m): 4 m 32
• Multiplier (n): 4 n 32 (even number only)
Fujitsu Microelectronics, Inc.
CE71L4
CE71L5
CE71L6
CE71L7
CE71L8
CE71L9
CE71LA
CE71LB
CE71LC
CE71LD
CE71LE
CE71T2
CE71T3
CE71T4
CE71T5
CE71T6
CE71T7
CE71T8
CE71T9
CE71TA
CE71TB
CE71TC
CE71TD
CE71TE
CE71TG
Frame
Frame
T-Series with 88µm Inline Pad Pitch and Wire Bonding
L-Series with 44µm Inline Pad Pitch and Au Bump
30 MS/s, 50 MS/s,
100 MS/s, 220 MS/s
Total Gates
Total Gates
1.110K
1.407K
1.559K
1.827K
2.088K
2.398K
3.040K
3.645K
5.152K
1,034K
1,469K
1,976K
2,513K
3,001K
3,506K
4,050K
5,043K
347K
524K
734K
845K
963K
356K
476K
677K
Total Pads
Total Pads
1,032
1,152
144
176
208
224
240
256
288
304
328
352
376
424
464
552
304
352
420
520
620
720
812
888
960
Signals
Signals
128
156
178
192
206
220
248
264
264
312
312
360
360
264
264
304
360
428
504
504
504
504
504
504
504
Memory Macros
• SRAM Compiler: single and dual port (1 R/W, 1R), up to
• ROM Compiler: up to 512K bits per block
• High-density single-port RAM 288K bits
• Register file (2R/W, 2R/2W), up to 4,608 bits
Phase-Locked Loops
• Analog: up to 250 MHz (622 MHz under development)
I/Os
• 2.5V, 3.3V, and 5V tolerant
• Slew-rate controlled
• CMOS, TTL, PCML, T-LVTTL, LVDS, PCI, SSTL,
SOC IP Cores
ARM 7TDMI Hard Macro
ARC 32-bit RISC
834/836 SPARClite Hard Macros
Oak DSP Hard Macro
10/100 MAC
64/256 QAM
MPEG2 Decoder/Demultiplexer
8VSB TV Demodulator
AC-3 Dolby Voice Decoder
JPEG Encoder and Decoder
PCI–33/66 MHz, 32/64-bit cores
USB Host Controller/Device
I
IDE (ATA3) Host Controller
Smart Card I/F
IRDA I/R Interface
More IPs are being added
2
C
72K bits per block, both BUS and Partial Write
GTL+, AGP, USB
Verilog Logic Simulators from
Cadence, Synopsys, and Mentor
VHDL/VITAL Logic
Simulators from Synopsys,
Cadence, and Mentor
Synthesis, power, DFT, and
STA tools from Synopsys
Other EDA tools
ASIC Design Kit and EDA Support
Verilog-XL, NC-Verilog,
VCS, Model-sim (Verilog)
VSS, Model-sim (VHDL), V-System,
Leapfrog
Design Compiler, Design Power, Test
Compiler, PrimeTime, MOTIVE, and
Sunrise TestGen
Chrysalis Design Verifyer and
Sente Watt Watcher