T8207-BAL-DT Agere Systems, Inc., T8207-BAL-DT Datasheet - Page 96
T8207-BAL-DT
Manufacturer Part Number
T8207-BAL-DT
Description
CelXpres ATM interconnect. Dry-bagget, tape & reel .
Manufacturer
Agere Systems, Inc.
Datasheet
1.T8207-BAL-DT.pdf
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CelXpres T8207
ATM Interconnect
14 Registers
Table 56. TX UTOPIA Clock Configuration (TXUCCF) (010Ch)
96
tx_utopia_clk_src_sel
tx_utopia_clk_div
tx_utopia_clk_en
Reserved
Reserved
Name
(continued)
Bit Pos. Type Reset
15:12
7:0
9:8
10
11
RW
RW
RW
RW
RO
01h
0
0
0
0
TX UTOPIA Clock Division. The selected TX UTOPIA clock
source is divided by the number programmed in these bits as
follows:
“00000000” = reserved
“00000001” = no division
“00000010” = divide by 2
“00000011” = divide by 3
“11111111” = divide by 255
These bits are meaningful only when the T8207 generates the
TX UTOPIA clock.
TX UTOPIA Clock Source Select. The source of the TX
UTOPIA clock is selected via these bits as follows:
“00” = cell bus write clock
“01” = reserved
“10” = pclk
“11” = mclk
These bits are meaningful only when the T8207 generates the
TX UTOPIA clock.
Reserved. Program to ‘0.’
TX UTOPIA Clock Enable. If this bit is ‘1,’ the T8207 gener-
ates the TX UTOPIA clock on the u_txclk pin. If this bit is ‘0,’
the u_txclk pin is configured as an input.
Reserved.
.
.
.
Description
Advance Data Sheet
September 2001
Agere Systems Inc.
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