PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 103

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
A separate H-MVIP interface consisting of a single signal is used to time division
multiplex the common channel signaling (CCS) for all T1s and E1s and
additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSED, is
not multiplexed with any other pins. CCSED can be used in parallel with the
Clock Slave:H-MVIP mode when SYSOPT[2:0] is set to “H-MVIP Interface” and
the ECCSEN bit in the T1/E1 Egress Serial Interface Mode Select register is set
to 1, a Clock Slave serial interface when SYSOPT[2:0] is set to “Serial Clock and
Data Interface with CCS H-MVIP Interface”, or the SBI Add bus when
SYSOPT[2:0] is set to “SBI Interface with CAS or CCS H-MVIP Interface” and
the ECCSEN bit is set to 1. The V5 channels in E1 mode can also be enabled
over CCSEN when the ETS15EN and ETS31EN bits in the T1/E1 Egress Serial
Interface Mode Select register are set to 1.
When accessing the CAS or CCS signaling via the H-MVIP interface in parallel
with the SBI interface a transmit signaling elastic store is used to adapt any
timing differences between the data interface and the CAS or CCS H-MVIP
interface.
Figure 20: Clock Master: Serial Data and H-MVIP CCS
When Clock Master: Serial Data and H-MVIP CCS mode is enabled, payload
data may be sourced through the egress serial interface, while common channel
signaling is sourced in parallel through the H-MVIP interface.
The H-MVIP egress interface multiplexes common channel signaling from up to
28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and
CMVFPC, and frame pulse, CMVFPB, for synchronization. Common channel
signaling over H-MVIP uses a Clock Slave serial interface, selected when
SYSOPT[2:0] is set to “Serial Clock and Data Interface with CCS H-MVIP
Interface”. CCSED is a single dedicated input pin sampled by CMV8MCLK,
used to time division multiplex the common channel signaling (CCS) for all T1s
Inputs Timed
to CMV8MCLK
ED[x] Inputs
Timed to
ICLK[x]
CMV8MCLK
ICLK[1:28]
CMVFPC
EFP[1:28]
ED[1:28]
CMVFP
CCSED
Interface
System
Egress
ESIF
ISSUE 1
T1-XBAS/E1-TRAN
Signaling Insertion,
Frame Generation,
Trunk Conditioning
BasicTransmitter:
Alarm Insertion,
Line Coding
90
Digital PLL
TJAT
TJAT
FIFO
TRANSMITTER
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3
Transmit CLK[1:28]
Transmit Data[1:28]