APL5912-KAC-TRL Anpec Electronics Corporation, APL5912-KAC-TRL Datasheet - Page 14

• Manufacturer Part Number: APL5912-KAC-TRL
• Description: 0.8V Reference Ultra Low Dropout (0.2V@5A) Linear Regulator
• Manufacturer: Anpec Electronics Corporation

APL5912
Application Information (Cont.)
Feedback Network (Cont.)
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
Copyright
Rev. A.6 - Jun., 2005
R1
C1
• Condition 3: Low ESR (eg. Ceramic Capacitors)
- Use equation (2) to calculate the R2.
- The C1 calculated from equation (4) must meet
- Use equation (2) to calculate the R2.
- Calculate the R1 as the following:
- Calculate the C1 as the following :
- The C1 calculated from equation (7) must meet
(pF)
C1
(k
please use the Condition 3.
the calculated C1.
If the C1
Select a proper R1
the calculated R1. The minimum selected R1
is equal to 1k
smaller than 1k or negative.
Select a proper C1
than the calculated C1.
If the C1
please use the Condition 2.
the following equation :
the following equation :
Where R1=R1
Where R1=R1
Where R1=R1
)
C1
(pF)
(pF)
(0.17
(5.9
0.033
ANPEC Electronics Corp.
(calculated)
(calculated)
5.1
ESR
ESR
1
(m
(m
1.25
(selected)
(calculated)
(calculated)
can not meet the equation (8),
ESR
can not meet the equation (5),
when the calculated R1 is
)
)
R1
(selected)
(selected)
50
8.5)
294)
V
(m
(k
OUT(V)
)
from equation (6)
from equation (3)
)
C
to be a little larger than
C
to be a little smaller
OUT(uF)
1
OUT(uF)
ESR
37.5
1
R1
(m
37.5
37.5
V
(k
)
OUT(V)
C
)
R1
OUT(uF)
V
V
(k
OUT(V)
OUT(V)
)
..
(5)
..
..
(8)
..
(6)
(7)
14
PCB Layout Considerations (See Figure 2)
1. Please solder the Exposed Pad and VIN together
2. Please place the input capacitors for VIN and VCNTL
3. Ceramic decoupling capacitors for load must be
4. To place APL5912 and output capacitors near the
5. The negative pins of the input and output capacitors
6. Please connect PIN 3 and 4 together by a wide
7. Large current paths must have wide tracks.
8. See the Typical Application
- Connect the one pin of R1 to the Pin 3 of APL5912
- Connect the one pin of C1 to the Pin 3 of APL5912
on the PCB. The main current flow is through the
exposed pad. The role of VIN is a voltage sense.
Refer Figure 3 to make a proximate topology.
pins near pins as close as possible.
placed near the load as close as possible.
load is good for performance.
and the GND pin of the APL5912 are connected to
the ground plane of the load.
track or plane on the Top layer.
APL5912.
- Connect the one pin of the R2 to the GND of
C
C N T L
A PL5912
VCNTL
G N D
V O U T
V O U T
VIN
F B
V
C N T L
C1
R2
Figure 2
R1
C
C
O U T
www.anpec.com.tw
IN
V
Load
V
OUT
IN