GA100358SCILF Integrated Circuit Systems, Inc., GA100358SCILF Datasheet

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GA100358SCILF

Manufacturer Part Number
GA100358SCILF
Description
IC FANOUT BUFFER SINGLE 8TSSOP TUBE
Manufacturer
Integrated Circuit Systems, Inc.
Datasheet
B
G
may have been attenuated, across a long trace, or may also
be used as a differential-to-LVPECL translator. The differen-
tial input can accept the following differential input types:
LVPECL, LVDS and CML. The device also has an output en-
able pin for debug/test purposes. When the output is disabled,
it drives differential LOW (Q = LOW, nQ = HIGH). The
ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP
or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on
space-constrained boards.
nPCLK
853001AG
HiPerClockS™
PCLK
ICS
LOCK
ENERAL
V
OE
BB
D
The ICS853001 is a 1:1 Differential LVPECL-
to-LVPE C L B u f fe r a n d a m e m b e r o f t h e
HiPerClock S ™ family of High Perfor mance
Clock Solutions from ICS. The ICS853001
may be used to regenerate LVPECL clocks which
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
LE
D Q
www.icst.com/products/hiperclocks.html
Q
nQ
1
F
P
1:1 Differential LVPECL-to-LVPECL / ECL buffer
1 LVPECL clock output pair
1 Differential LVPECL PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
Maximum output frequency: >2.5GHz
Part-to-part skew: 100ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
V
ECL mode operating voltage supply range:
V
-40°C to 85°C ambient operating temperature
Lead-Free package RoHS compliant
EATURES
IN
2.5V, 3.3V, 5V LVPECL/ECL B
CC
CC
= 2.375V to 5.25V, V
= 0V, V
A
3.90mm x 4.90mm x 1.37mm package body
SSIGNMENT
3mm x 3mm x 0.95mm package body
EE
1:1, D
= -5.25V to -2.375V
8-Lead TSSOP, 118 mil
V
V
nQ
CC
EE
Q
ICS853001
ICS853001
8-Lead SOIC
IFFERENTIAL
M Package
G Package
EE
Top View
1
2
3
4
Top View
= 0V
8
7
6
5
OE
PCLK
nPCLK
V
ICS853001
BB
LVPECL-
REV. A JANUARY 29, 2005
UFFER
TO
-

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GA100358SCILF Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS853001 is a 1:1 Differential LVPECL- ICS to-LVPE HiPerClockS™ ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage (LVPECL mode Negative Supply Voltage, V -6V (ECL mode Inputs, V (LVPECL mode) -0. Inputs, V (ECL mode) 0.5V ...

Page 4

Integrated Circuit Systems, Inc. T 3D. LVPECL DC C ABLE HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...

Page 6

Integrated Circuit Systems, Inc. P ARAMETER LVPECL V EE -3.25V to -0.375V UTPUT OAD EST IRCUIT nQx PART 1 Qx nQy PART sk(pp ART TO ...

Page 7

Integrated Circuit Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level V generated from the device ...

Page 8

Integrated Circuit Systems, Inc. T 2.5V LVPECL O ERMINATION FOR Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat- ing 2V. For V = 2.5V, the ...

Page 9

Integrated Circuit Systems, Inc. T 3.3V LVPECL O ERMINATION FOR The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance ...

Page 10

Integrated Circuit Systems, Inc. LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show interface CMR examples for ...

Page 11

Integrated Circuit Systems, Inc PPLICATION CHEMATIC XAMPLE Figure 6 shows an example of ICS853001 application schematic. In this example, the device is operated at V decoupling capacitor should be located as close as possible to the power ...

Page 12

Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS853001. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853001 is the sum of the core ...

Page 13

Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. F IGURE T o calculate worst case ...

Page 14

Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T 6B ABLE VS IR LOW ABLE JA Single-Layer PCB, JEDEC ...

Page 15

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T 7A ABLE ACKAGE IMENSIONS ...

Page 16

... The aforementioned trademark, HiPerClockS™ trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use ...

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