A3992SBT- Allegro MicroSystems, Inc., A3992SBT- Datasheet - Page 7

• Manufacturer Part Number: A3992SBT-
• Description: DMOS Dual Full-Bridge Microstepping PWM Motor Driver
• Manufacturer: Allegro MicroSystems, Inc.

A3992
D14 – D15 Synchronous Rectifi cation.
different modes of operation (see Synchronous Rectifi -
cation in the Functional Description section):
VREG.
0.22 μF capacitor to ground. This internally gener-
ated supply voltage is used to run the sink side DMOS
outputs. VREG is internally monitored and in the
case of a fault condition, the outputs of the device are
disabled.
Current Regulation.
by analog input to the REF terminal, or via the internal
2 V precision reference. The choice of reference volt-
age and selection of sense resistor set maximum trip
current, as follows:
Microstepping current levels are set according to the
following equations:
where DAC is the input code, 1 to 63 (Word 0, D1 to
D12), and Range is 4 or 8, as selected by Word 0, D18.
Programming a DAC input code to 0 disables the cor-
responding bridge, and results in minimum load current.
PWM Timer Function.
mable via the serial port to provide fi xed off-time
D15
0
0
1
1
The VREG pin should be decoupled with a
I
I
TRIPMAX
TRIP
V
DAC
= V
D14
0
1
0
1
= ((1+DAC) × V
DAC
= V
REF
/ (Range × R
The reference voltage can be set
The PWM timer is program-
/ (Range × R
Synchronous Rectifier
Allegro defined use
Disabled
Passive
SENSE
REF
Active
) / 64 ,
SENSE
) , and
Functional Description
2 bits set the
) .
Microstepping PWM Motor Driver
D16, D17 (Reserved).
They should be programmed to 0 during normal op-
eration.
D18 Idle Mode.
power Idle mode by writing a 0 to D18. The outputs
are disabled, the charge pump turned off, and the de-
vice consumes a lower supply current. The undervolt-
age monitor circuit remains active.
PWM signals to the control block. In mixed decay
mode, the fi rst portion of the off-time operates in fast
decay, until the fast decay time count is reached, fol-
lowed by slow decay for the remainder of the fi xed
off-time. If the fast decay time is set longer than the off-
time, the device effectively operates in fast decay mode.
Oscillator.
input, typically 4 MHz. The A3992 can be confi gured
to select either the 4 MHz internal oscillator or, if
more precise accuracy is required, an external clock
can be connected to the OSC terminal. If an external
clock is used, 3 internal divider choices are selectable
via the serial port to allow fl exibility in choosing f
based on available system clocks. If the internal oscil-
lator option is used, the absolute accuracy is dependent
on process variation of resistance and capacitance.
A precision resistor can be connected from the OSC
terminal to V
frequency is calculated as:
If the internal oscillator is used without the external re-
sistor the OSC terminal should be connected to GND.
The PWM timer is based on an oscillator
DMOS Dual Full-Bridge
DD
f
OSC
to further improve the tolerance. The
The device can be put into the low-
= 204 × 10
2 bits reserved for testing.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
9
/ R
OSC .
OSC
7