A3950SEU-T Allegro MicroSystems, Inc., A3950SEU-T Datasheet - Page 11

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A3950SEU-T

Manufacturer Part Number
A3950SEU-T
Description
A3950 4X4 QFN
Manufacturer
Allegro MicroSystems, Inc.
Datasheet
A3950
17X
0.08
D
0.40 ±0.10
C
0.30 ±0.05
1
2
2
1
16
16
0.65
A
4.00 ±0.15
2.15
B
EU Package, 16 Pin QFN with Exposed Thermal Pad
2.15
4.00 ±0.15
0.75 ±0.05
SEATING
PLANE
C
DMOS Full-Bridge Motor Driver
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
D
C
For Reference Only
(reference JEDEC MO-220WGGC)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
identifier appearance at supplier discretion)
Coplanarity includes exposed thermal pad and terminals
Reference land pattern layout (reference IPC7351
QFN65P400X400X80-17BM)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
1.15
1
2
C
16
PCB Layout Reference View
2.15
3.80
0.35
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
0.65
2.15
3.80
11

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