A3932SEQ-TTR Allegro MicroSystems, Inc., A3932SEQ-TTR Datasheet - Page 8

• Manufacturer Part Number: A3932SEQ-TTR
• Description: IC MOSFET DRVR 5V DUAL HI/LO SIDE 3-PHASE BRDG 32PLCC T/R
• Manufacturer: Allegro MicroSystems, Inc.

in the external MOSFETs, the A3932 control logic turns on the
appropriate low-side and high-side driver during the load-
current recirculation, PWM-off cycle. Synchronous
rectification allows current to flow through the MODE-selected
MOSFET, rather than the body diode, during the decay time.
The body diodes of the SR power MOSFETs will conduct only
during the dead time required at each PWM transition.
high- or low-side turn off and the next turn-on event to prevent
cross conduction. The potential for cross conduction occurs
with synchronous rectification, direction changes, PWM, or
after a bootstrap capacitor charging cycle. The dead time is set
by a resistor (R
(+5 V) and can be set between 100 ns and 5.5 s.
and 470 k . At 25 C,
For predicting worst case, over voltage and temperature
extremes,
For comparison with I
where (nominal values) V
R
ground (V
10 A) current source.
resistance determines the selection of the dead-time resistor.
The dead time should be made long enough to cover the
variation of the MOSFET gate capacitance and series gate
resistance (both external and internal to the A3932) tolerances.
for the gate-drive circuit. As the gates are driven high they will
require current from an external capacitor to support the
transients. This capacitor should be placed as close as possible
to the V
larger than the bootstrap capacitor.
int
3932
THREE-PHASE POWER
MOSFET CONTROLLER
= 500 .
The following equations are valid for R
Rather than use R
The choice of power MOSFET and external series gate
t
t
t
dead
dead
REG
dead
DEAD
(nom, ns) = 37 + (11.9 x 10
(max, ns) = 63 + (17.2 x 10
(min, ns) = 10 + (6.55 x 10
terminal. Its value should be at least 20 times
I
It is required to have a dead-time delay between a
DEAD
dead
The internal reference, V
= 0 V), which activates an internal (I
) between the DEAD terminal and LCAP
= (V
DEAD
dead
LCAP
LCAP
values near 470 k , set DEAD =
test currents,
– V
= 5 V, V
To reduce power dissipation
be
)/(R
-3
-3
-3
dead
be
REG
x (R
x (R
x (R
= 0.7 V at 25 C, and
+ R
dead
, supplies current
dead
dead
dead
int
between 5.6 k
)
+ 350))
+ 500))
+ 650))
DEAD
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
=
should be connected between LCAP and AGND as close to the
device terminals as possible.
features:
1) Bootstrap Circuit. The bootstrap capacitor is charged
whenever a low-side MOSFET is on, Sx output goes low, and
the load current recirculates. This happens constantly during
normal operation. The high-side MOSFET will not be allowed
to turn on before the charging has decayed to less than
approximately 9 mA. No fault will be registered.
(100% duty cycle operation) its charge pump is designed to
maintain V
gate driver) < 10 A.
2) Hall Invalid. Illegal codes for the HALL inputs (000 or
111) will force a fault and coast the motor. Noisy Hall lines
may cause double TACH pulses and, therefore, code errors that
produce faults. Additional external pullup loading and filtering
may be required depending on the system.
3) VREG Undervoltage. An internal regulator supplies the
low-side gate driver and the bootstrap charge current. It is critical
to ensure that V
the outputs. The undervoltage circuit is active during power-up
and will force a motor coast condition (all gate drives, GHx and
GLx = 0) until V
4) Thermal Shutdown. A junction temperature greater than
165 C will signal a fault and coast the motor (all gate drives
LOW). If the junction temperature then falls to less than 155 C
(hysteresis), the fault will be cleared.
5) Motor Lead Shorted to Ground. The A3932 will signal a
fault if a motor lead is shorted to ground. A short to ground is
assumed after a high side is turned on and greater than 2 V is
measured between the drain (V
the high-side power MOSFET. This fault is cleared at the
beginning of each commutation. If a stalled motor results from
a fault, the fault can only be cleared by toggling the RESET
terminal or by a power-up sequence.
Additionally, a 0.1 F (or larger) decoupling capacitor
When a phase’s high-side driver is on for a long time
GS
> 9 V on the bridge FET if I
REG
REG
is at the proper level before enabling any of
is greater than approximately 9.7 V.
The A3932 has several protection
BB
) and source (SA/SB/SC) of
GHx
(the load on the
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