SD1010-1199A N/A, SD1010-1199A Datasheet - Page 27

• Manufacturer Part Number: SD1010-1199A
• Description: Analog-Interface XGA TFT LCD Display Controller
• Manufacturer: N/A

Minimum pixels per line
Maximum link off time
Maximum refresh rate
Data high threshold
November, 1999
Revision B
Data low threshold
Reserved Entries
Calibration mode
PWM unit delay
Maximum input
Maximum VBP
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Edge threshold
LCD polarity
frequency
for LCD
16
22
16
11
8
8
8
8
8
2
8
4
25AH-25BH The unit delay used in the external PWM delay circuitry.
25CH-25EH Maximum time when input VSYNC is off before the
25FH-260H Maximum refresh rate supported by the LCD panel.
222H-255H Set to all 0 or all 1 (reserved)
262H-263H Minimum number of pixels per line for LCD panel
259H [1:0] Selects different operation modes of internal phase
264H[3:0]
221H
256H
257H
258H
261H
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0: disable SYNC polarity based mode detection
bit 0: 640x350
bit 3: 640x480
bit 6: 1024x768
bit 9: res mode3
bit 12: res mode6 bit 13: res mode7
The maximum vertical back porch for input video
Low water mark for valid data.
If the data is smaller than this threshold, it is considered
LOW internally
High water mark for valid data.
If the data is larger than this threshold, it is considered
HIGH internally
Minimum difference between the data value of two
adjacent pixels to be considered as an edge
calibration. The selection criterion is as follows:
0: when input video signal has large overshot,
1: when input video signal has median overshot,
2: when input video signal has normal overshot,
3: when input video signal has no overshot,
If the free-running clock is 1MHz, and the intended unit
delay is 0.2 ns (= 5,000MHz), then a value of
5,000MHz/1MHz = 5,000 is used here.
LINK_DWN pin turns ON (unit: clock period of the free
running clock). If the free-running clock is 1MHz, and the
intended maximum time is 1 second, then a value of
1,000,000 s/ 1 s = 1,000,000 is used here.
If the intended maximum refresh rate is 75Hz, and the
free-running clock is 1MHz, then a value of
1000000/75=133,333 is used here
Maximum source clock rate supported by the SD1010
(unit: frequency of free-running clock).
If the intended maximum clock rate is 60MHz, and the
free-running clock is 1MHz, then a value of 60 is used
here.
If the input signal has a higher frequency than this value,
the VCLK0_X status bit will turn ON.
Controls the polarity of output VSYNC,
HSYNC, clock and display enable:
active high, 1: clock active low
Bit1: 0: HSYNC active low, 1: HSYNC active high
Bit2: 0: VSYNC active low, 1: VSYNC active high
it results in longest calibration time
it results in long calibration time
it results in normal calibration time
(recommended)
it results in shortest calibration time
bit 10: res mode4
bit 7: res mode1
bit 1: 640x400
bit 4: 800x600
bit 11: res mode5
bit 2: 720x400
bit 5: 832x624
bit 8: res mode2
Bit0: 0: clock
SD1010A
27