MSC7119 Freescale Semiconductor / Motorola, MSC7119 Datasheet - Page 42

• Manufacturer Part Number: MSC7119
• Description: Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Design Considerations
3.2
This section outlines the MSC7119 power considerations: power supply, power sequencing, power planes, decoupling, power
supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power
consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
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Power Supply. The MSC7119 requires four input voltages, as shown in Table 32.
You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility
with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%)
across V
reference voltages supply the DDR memory controller block. The memory voltage is supplied with 2.5 V across V
and
V
voltage supply requirements.
Power sequencing. One consequence of multiple power supplies is that the voltage rails ramp up at different rates when
power is initially applied. The rates depend on the power supply, the type of load on each power supply, and the way
different voltages are derived. It is extremely important to observe the power up and power down sequences at the
board level to avoid latch-up, forward biasing of ESD devices, and excessive currents, which all lead to severe device
damage. The correct power-up sequence is as follows:
— Turn on the highest supply first (3.3 V).
— Turn on the 2.5 V supply.
— Turn on the lowest supply last (1.2 V).
The correct power-down sequence is as follows:
— Turn off the lowest supply first (1.2 V).
— Turn off the 2.5 V supply.
— Turn off the highest supply last (3.3 V).
At any instant during power-up and power-down, the 2.5 V supply must maintain a differential of +0.7 V or more
below the 3.3 V supply. Also, at any instant, the 1.2 V supply must maintain a differential of +0.7 V or more below the
2.5 V supply, as shown in
Core
Memory
Reference
I/O
DDM
GND
Power Supply Design Considerations
. Refer to the JEDEC standard JESD8 (Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory
DDC
. The reference voltage is supplied across V
and
Voltage
GND
and the I/O section is supplied with 3.3 V (± 10%) across V
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Figure
30. The power-down sequence is not as critical as the power-up sequence.
Table 32. MSC7119 Voltages
REF
Symbol
V
V
V
V
DDIO
DDM
DDC
REF
and
GND
and must be between 0.49 × V
DDIO
and
Freescale Semiconductor
GND.
Value
1.25 V
1.2 V
2.5 V
3.3 V
DDM
The memory and
and 0.51 ×
DDM