HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet
HFA3863IN96
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HFA3863IN96 Summary of contents
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... PCMCIA board applications pin-compatible with the HFA3861B. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HFA3863IN - TQFP HFA3863IN96 - Tape and Reel Pinout GNDd DDD SD 3 ...
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Typical Application Diagram ANTSEL HFA3683A RF/IF CONV (FN4634) ∑ PLL RF LO REF IN HFA3963 RFPA (FN TBD) 44MHz MCLK T/Rsw DIFFERENTIAL SIGNALS TABLE 1. TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3863 The four-digit file numbers are shown in the ...
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Pin Descriptions NAME PIN TYPE I/O V (Analog) 12, 17, 22, Power DDA 31 V (Digital 37, 41, Power DDD 57 GNDa 9, 15, 20, Ground (Analog) 25, 28 GNDd (Digital 36, 43, Ground 56 V ...
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Pin Descriptions (Continued) NAME PIN TYPE I/O MD_RDY 54 O RX_PE I/O SCLK 4 I SDI TEST 7:0 51, 50, 49, I/O 48, 47, 46, 45, 44 RESET ...
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HFA3863 RXI AGC ANALOG RXQ TXI INPUTS AGC TXQ TXD V A/D REF TXCLK I REFERENCE REF TX_RDY RXD TX_PE POWER RXC RX_PE DOWN MD_RDY SIGNALS RESET TEST TEST SCLK PORT R/W ANT_SEL SDI FIGURE 1. EXTERNAL ...
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TX Port The transmit data port accepts the data that needs to be transmitted serially from an external data source. The data is modulated and transmitted as soon received from the external data source. The serial data ...
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RXCLK is an output from the HFA3863 and is the clock for the serial demodulated data on RXD. MD_RDY is an output from the HFA3863 and it may be set to go active after the SFD or CRC fields. Note ...
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HFA3683 Power Down Modes The power consumption modes of the HFA3863 are controlled by the following control signals. Receiver Power Enable (RX_PE, pin 61), which disables the receiver when inactive. Transmitter Power Enable (TX_PE, pin 62), which disables the transmitter ...
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TABLE 4. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz DATA A/D SAMPLE CLOCK MODULATION (MHz) DBPSK 22 DQPSK 22 CCK 22 CCK 22 802.11 DSSS BPSK 1Mbps BARKER DATA 1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE) ...
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In the long preamble mode, the device uses a synchronization preamble of 128 symbols along with a header that includes four fields. The preamble is all 1's (before entering the scrambler) plus a start frame delimiter (SFD). The actual transmitted ...
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PREAMBLE (SYNC) SFD 128/56 BITS 16 BITS PREAMBLE Scrambling is done by division with a prescribed polynomial as shown in Figure 9. A shift register holds the last quotient and the output is the exclusive or of the data and ...
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The phase ϕ1 modifies ...
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AGC state machine runs asynchronously with respect to slot times. SQ1 becomes active only when a spread signal with the proper PN code has been detected, and the peak correlation amplitude to sidelobe ratio exceeds a set threshold, ...
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Pad Releasing (RF Chip High Gain): If the AGC is not locked onto a packet and the attenuation accumulator sum falls below the programmable threshold (CR27), the pad will release. This is for the case where a noise spike ...
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SQ1’s will cause the part to finish the acquisition phase and enter the tracking phase. Prior to initial acquisition the NCO is inactive (0Hz) and carrier phase measurement are done on a symbol by symbol basis. After acquisition, coherent ...
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V (ANALOG) DD (12, 17, 22, 31) I (21) REF V (16) REF 6-BIT TX_AGC_IN (18) ADC 6-BIT TX_IF_AGC (35) DAC ANTSEL (39) ANTSEL (40) (62) TX_PE FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION Channel Matched Filter (CMF) Description The ...
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I and one for the Q Channel. The same Barker sequence is always used for both I and Q correlators. These correlators are time invariant matched filters otherwise known as parallel correlators. They use one sample ...
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V (ANALOG) DD (12, 17, 22, 31) RX_IF_DET (19) RX_IF_AGC (34) 6-BIT RX-RF-AGC (38) DAC DIVERSITY ANT SEL (39, 40) CONTROL 6-BIT RXI (10, 11) A/D 6 6-BIT RXQ (13, 14) A/D 6 COHERENT TIMING INTEGRATOR ANTSEL (40) ANTENNA SWITCH ...
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Data Demodulation in the CCK Modes In this mode, the demodulator uses complementary code keying (CCK) modulation for the two highest data rates slaved to the low rate processor which it depends on for acquisition of initial timing ...
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CCK modes. The losses in both figures include RF and IF radio losses; they do not reflect the HFA3863 losses alone. The HFA3863 baseband processing losses from theoretical are, by themselves, a small percentage of the overall ...
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Signal Quality Estimate A signal quality measure is available on CR51 for use by the MAC. This measure is the SNR in the carrier tracking loop and can be used to determine when the demodulator is working near to the ...
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TABLE 10. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY CONFIGURATION REGISTER CR0 Part/Version Code CR1 I/O Polarity CR2 RX Configure CR3 TX Preamble Length for Short Preamble CR4 TX Preamble Length for Long Preamble CR5 TX Signal Field CR6 TX ...
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TABLE 10. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY (Continued) CONFIGURATION REGISTER CR45 False Alarm Rate Scale Factor CR46 Preamble Timeline Control CR47 Acquisition Control CR48 Scrambler Seed for Long Preamble CR49 Read Only Register Mux Control For Registers 50 ...
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Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Part Code 3 = HFA3863 series Bit 3:0 Version ...
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CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD Bits 7:5 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 4 TX/RX filter / CMF weight select US. 1 ...
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CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE Bit 7 AGC freeze during packet Disable (do not disable unless MAC can handle baseband processor aborting during MPDU reception Enable. Bit 6 CIR estimate/ Dot product clock ...
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CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued) Bit 3 Q DAC clock enable disable. Bit 2 RF A/D clock enable disable. Bit 1 I A/D clock ...
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CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 (Continued) Bit 3 Enable test bus into RX and TX DAC (if below bit normal enable. Bit 2 Enable RF A/D into RX ...
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CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA Bits 7 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 6:0 AGC look up table data, unsigned. CONFIGURATION REGISTER 24 ADDRESS ...
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CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR Bits 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 5:0 Carrier Sense 2 (CS2) scale factor (0–7.875 range) ...
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CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2 (Continued) Bit 2 Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block normal chip operation loop back disabled loop back enabled, A/D and ...
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CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE/HEADER LEAD COEFFICIENT Bit 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 5:0 Preamble Lead Coefficient (0–4 range) (000000–100000). CONFIGURATION REGISTER ADDRESS 42 ...
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CONFIGURATION REGISTER ADDRESS 51 (66h) R SIGNAL QUALITY MEASURE Bit 7:0 a: NOISEfloorAntA [7:0] unsigned, range 0–255. b: measures signal quality based on the SNR in the carrier tracking loop. CONFIGURATION REGISTER ADDRESS 52 (68h) R RECEIVED SIGNAL FIELD Bit ...
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CONFIGURATION REGISTER ADDRESS 63 (80h) R RECEIVE STATUS Bit 7:6 a&b: signal field value (HRfieldmatch/QPSKwd_OK 5. 11. Bit 5 a&b: SFD found. Bit 4 a&b: Short preamble detected. Bit 3 ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V PARAMETER TX_CLK to TX_PE Inactive (11Mbps) TX_RDY Inactive to Last Chip of MPDU Out TXD Modulation Extension RX_PE Inactive Width RX_CLK Period (11Mbps Mode) RX_CLK Width Hi or Low (11Mbps Mode) RX_CLK to RXD MD_RDY to ...
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I and Q A/D AC Electrical Specifications ) PARAMETER Full Scale Input Voltage (V ) P-P Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) NOTE: 20. Not tested, but characterized at initial design and at major process/design ...
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Waveforms (Continued) TX_PE OUT OUT TXRDY TX_CLK TXD t RLP RX_PE MD_RDY RX_CLK RXD CCA, RSSI NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...