STPCD01 STMicroelectronics, STPCD01 Datasheet - Page 12

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STPCD01

Manufacturer Part Number
STPCD01
Description
STPC CLIENT DATASHEET - PC COMPATIBLE EMBEDED MICROPROCESSOR
Manufacturer
STMicroelectronics
Datasheet

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PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
12/61
BASIC CLOCKS RESETS & XTAL
SYSRSTI#
SYSRSTO#*
XTALI
XTALO
PCI_CLKI
PCI_CLKO
ISA_CLK
ISA_CLK2X
OSC14M*
HCLK*
DEV_CLK
GCLK2X*
DCLK*
DCLK _DIR*
V
MEMORY INTERFACE
MA[11:0]
RAS#[3:0]
CAS#[7:0]
MWE#
MD[63:0]*
PCI INTERFACE
AD[31:0]*
CBE[3:0]*
FRAME#*
TRDY#*
IRDY#*
STOP#*
DEVSEL#*
PAR*
SERR#*
LOCK#
PCI_REQ#[2:0]*
PCI_GNT#[2:0]*
PCI_INT[3:0]*
VDD5
ISA AND IDE COMBINED ADDRESS/DATA
LA[23:22]*/ SCS3#,SCS1#
LA[21:20]*/ PCS3#,PCS1#
LA[19:17]*/ DA[2:0]
RMRTCCS#* / DD[15]
KBCS#* / DD[14]
Note; * denotes theat the pin is V
DD
_xxx_PLL
Signal Name
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
5T
System Reset / Power good
Reset Output to System
14.3MHz External Oscillator Input
14.3MHz External Oscillator Input
33MHz PCI Input Clock
33MHz PCI Output Clock (from internal PLL)
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x 2 Output - Multiplexer Select Line For IPC
ISA bus synchronisation clock
Host Clock (Test)
24MHz Peripheral Clock (floppy drive)
80MHz Graphics Clock
135MHz Dot Clock
Dot Clock Direction
Power Supply for PLL Clocks
Memory Address
Row Address Strobe
Column Address Strobe
Write Enable
Memory Data
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
Target Ready
Initiator Ready
Stop Transaction
Device Select
Parity Signal Transactions
System Error
PCI Lock
PCI Request
PCI Grant
PCI Interrupt Request
5V Power Supply for PCI ESD protection
Unlatched Address (ISA) / Secondary Chip Select (IDE)
Unlatched Address (ISA) / Primary Chip Select (IDE)
Unlatched Address (ISA) / Address (IDE)
ROM/RTC Chip Select / Data Bus bit 15 (IDE)
Keyboard Chip Select / Data Bus bit 14 (IDE)
(see Section 4. )
Issue 2.2 - October 13, 2000
Description
Qty
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