ADSP-21060LKB-160 Analog Devices, ADSP-21060LKB-160 Datasheet

ADSP-21060LKB-160

Manufacturer Part Number

ADSP-21060LKB-160

Description

Manufacturer

Analog Devices

Datasheets

1.ADSP-21060LKB-160.pdf (64 pages)

2.ADSP-21060LKB-160.pdf (47 pages)

Specifications of ADSP-21060LKB-160

Case

BGA

03+

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Bonase Electronics (HK) Co., Limited

Part Number:

ADSP-21060LKB-160

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BOSTOCK HK LIMITED

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ADSP-21060LKB-160

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SUMMARY

High performance signal processor for communications,

Super Harvard Architecture

32-bit IEEE floating-point computation units—multiplier,

Dual-ported on-chip SRAM and integrated I/O peripherals—a

Integrated multiprocessing features

240-lead thermally enhanced MQFP_PQ4 package, 225-ball

RoHS compliant packages

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

graphics and imaging applications

4 independent buses for dual data fetch, instruction fetch,

ALU, and shifter

complete system-on-a-chip

plastic ball grid array (PBGA), 240-lead hermetic CQFP

package

and nonintrusive I/O

DAG1

CONNECT

MULT

(PX)

BUS

DAG2

CORE PROCESSOR

DATA

FILE

DM ADDRESS BUS

40-BIT

PM ADDRESS BUS

PM DATA BUS

DM DATA BUS

TIMER

SHIFTER

BARREL

SEQUENCER

PROGRAM

INSTRUCTION

CACHE

40/32

48-BIT

ALU

Figure 1. Functional Block Diagram

ADDR

PROCESSOR PORT

ADDR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel : 781.329.4700

Fax: 781.461.3113

KEY FEATURES—PROCESSOR CORE

40 MIPS, 25 ns instruction rate, single-cycle instruction

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse

Efficient program sequencing with zero-overhead looping:

IEEE JTAG Standard 1149.1 Test Access Port and on-chip

32-bit single-precision and 40-bit extended-precision IEEE

DUAL-PORTED BLOCKS

TWO INDEPENDENT

DATA

execution

addressing)

Single-cycle loop setup

emulation

floating-point data formats or 32-bit fixed-point data

format

DUAL-PORTED SRAM

DATA BUFFERS

STATUS AND

REGISTERS

DATA

(MEMORY

MAPPED)

CONTROL,

IOP

DATA

I/O PROCESSOR

DATA

I/O PORT

IOD

ADDR

SERIAL PORTS

CONTROLLER

LINK PORTS

ADDR

IOA

DMA

(2)

(6)

SHARC Processor

MULTIPROCESSOR

ADDR BUS

INTERFACE

DATA BUS

EXTERNAL

HOST PORT

EMULATION

MUX

PORT

MUX

TEST AND

JTAG

www.analog.com

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